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preliminary user?s manual pd78f9221 pd78F9222 78k0s/ka1+ 8-bit single-chip microcontrollers ? printed in japan document no. u16898ej1v0ud00 (1st edition) date published november 2003 n cp(k) 2003 www..net
preliminary user?s manual u16898ej1v0ud 2 [memo] www..net
preliminary user?s manual u16898ej1v0ud 3 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. windows and windows nt are either re gistered trademarks or trademarks of microsoft corporation in the united states and/or other countries. pc/at is a trademark of internati onal business machines corporation. hp9000 series 700 and hp-ux are trad emarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademar ks of sun microsystems, inc. superflash ? is a registered trademark of silicon storage technology, inc. in several countries including the united states and japan. www..net
preliminary user?s manual u16898ej1v0ud 4 caution: this product uses superflash ? technology licensed from s ilicon storage technology, inc. the information contained in this document is being issued in advance of the production cycle for the product. the parameters for the product may change before final production or nec electronics corporation, at its own discretion, may withdraw the product prior to its production. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of an nec electronics products depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. ? ? ? ? ? ? ? m5d 02. 11-1 the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific": www..net
preliminary user?s manual u16898ej1v0ud 5 regional information ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [global support] http://www.necel.com/en/support/support.html nec electronics america, inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 nec electronics hong kong ltd. hong kong tel: 2886-9318 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-558-3737 nec electronics shanghai, ltd. shanghai, p.r. china tel: 021-6841-1138 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 nec electronics singapore pte. ltd. novena square, singapore tel: 6253-8311 j03.4 n ec electronics (europe) gmbh duesseldorf, germany tel: 0211-65 03 01 sucursal en espa?a madrid, spain tel: 091-504 27 87 vlizy-villacoublay, france tel: 01-30-67 58 00 succursale fran?aise filiale italiana milano, italy tel: 02-66 75 41 branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 tyskland filial taeby, sweden tel: 08-63 80 820 united kingdom branch milton keynes, uk tel: 01908-691-133 some information contained in this document may vary from country to country. before using any nec electronics product in your application, piease contact the nec electronics office in your country to obtain a list of authorized representatives and distributors. they will verify: www..net
preliminary user?s manual u16898ej1v0ud 6 introduction target readers this manual is intended for user engineer s who wish to understand the functions of the 78k0s/ka1+ in order to desi gn and develop its application systems and programs. the target devices are t he following subseries products. ? 78k0s/ka1+: pd78f9221, 78F9222 purpose this manual is intended to give users on understanding of the f unctions described in the organization below. organization two manuals are available for the 78k0s /ka1+: this manual and the instruction manual (common to the 78k/0s series). 78k0s/ka1+ user?s manual 78k/0s series instructions user?s manual ? pin functions ? internal block functions ? interrupts ? other internal peripheral functions ? electrical specifications (target) ? cpu function ? instruction set ? instruction description how to use this manual it is assumed that the readers of this manual have general knowledge of electrical engineering, logic circuits, and microcontrollers. ? to understand the overall functions of 78k0s/ka1+ read this manual in the order of the contents . ? how to read register formats the name of a bit whose number is enclosed with <> is reserved in the assembler and is defined in the c compiler by the header file sfrbit.h. ? to learn the detailed functions of a register whose register name is known see appendix c register index . ? to learn the details of the instru ction functions of the 78k/0s series refer to 78k/0s series instructions user?s manual (u11047e) separately available. ? to learn the electrical specific ations (target) of the 78k0s/ka1+ see chapter 20 electrical spec ifications (target values) . www..net
preliminary user?s manual u16898ej1v0ud 7 conventions data significance: higher digits on the left and lower digits on the right active low representation: (overscore over pin or signal name) note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numerical representation: binary ... or b decimal ... hexadecimal ... h related documents the related documents indicated in this pub lication may include preliminary versions. however, preliminary versions are not marked as such. documents related to devices document name document no. 78k0s/ka1+ subseries user?s manual this manual 78k/0s series instructions user?s manual u11047e documents related to developmen t software tools (user?s manuals) document name document no. operation u14876e language u14877e ra78k0s assembler package structured assembly language u11623e operation u14871e cc78k0s c compiler language u14872e id78k series integrated debugger ver. 2.30 or later operation (windows tm based) u15185e project manager ver. 3.12 or later (windows based) u14610e documents related to development hardware tools (user?s manuals) document name document no. ie-78k0s-ns in-circuit emulator u13549e ie-78k0s-ns-a in-circuit emulator u15207e caution the related docum ents listed above are subject to change without notice. be sure to use the latest version of each document for designing. www..net
preliminary user?s manual u16898ej1v0ud 8 documents related to flash memory writing document name document no. pg-fp4 flash memory progr ammer user?s manual u15260e other related documents document name document no. semiconductor selection guide - products and packages - x13769x semiconductor device mount manual note quality grades on nec semiconductor devices c11531e nec semiconductor device reliability/quality control system c10983e guide to prevent damage for semiconductor devi ces by electrostatic discharge (esd) c11892e note see the ?semiconductor device mount manual? webs ite (http://www.necel.com/pkg/en/mount/index.html). caution the related docum ents listed above are subject to change without notice. be sure to use the latest version of each document for designing. www..net
preliminary user?s manual u16898ej1v0ud 9 contents chapter 1 overview.......................................................................................................... ............... 14 1.1 features ................................................................................................................... ................... 14 1.2 application fields ......................................................................................................... ............. 14 1.3 ordering information ....................................................................................................... .......... 15 1.4 pin configuration (top view) ................................... ............................................................ .... 15 1.5 78k0s/kx1+ product lineup....................................... ........................................................... ... 16 1.6 block diagram.............................................................................................................. .............. 17 1.7 functional outline ......................................................................................................... ............ 18 chapter 2 pin funct ions.................................................................................................... ........... 19 2.1 pin function list .......................................................................................................... .............. 19 2.2 pin functions .............................................................................................................. ............... 21 2.2.1 p20 to p23 (por t 2)...................................................................................................... ................ 21 2.2.2 p30, p31, and p34 (p ort 3) ............................................................................................... .......... 21 2.2.3 p40 to p45 (por t 4)...................................................................................................... ................ 22 2.2.4 p121 to p123 (por t 12)................................................................................................... ............. 22 2.2.5 p130 (port 13) ........................................................................................................... .................. 22 2.2.6 reset .................................................................................................................... .................... 22 2.2.7 x1 and x2 ................................................................................................................ ................... 22 2.2.8 av ref ............................................................................................................................... ............ 22 2.2.9 v dd ............................................................................................................................... ............... 23 2.2.10 v ss ............................................................................................................................... ................ 23 2.3 pin i/o circuits and connection of unused pins ... ................................................................ 23 chapter 3 cpu architecture........................................ ......................................................... ..... 25 3.1 memory space................................................................................................................... ......... 25 3.1.1 internal progr am memory space............................................................................................ ...... 27 3.1.2 internal dat a memory space ............................................................................................... ......... 27 3.1.3 special function register (s fr) area ..................................................................................... ...... 28 3.1.4 data memo ry addre ssing ................................................................................................... ......... 28 3.2 processor registers ............................................................................................................ ...... 30 3.2.1 control regist ers ........................................................................................................ .................. 30 3.2.2 general-pur pose regi sters................................................................................................ ........... 32 3.2.3 special functi on register s (sfrs) ........................................................................................ ........ 33 3.3 instruction address addressing ................................... .......................................................... .36 3.3.1 relative addre ssing ...................................................................................................... ............... 36 3.3.2 immediat e addre ssing ..................................................................................................... ............ 37 3.3.3 table indi rect addr essing ................................................................................................ ............ 37 3.3.4 register addre ssing ...................................................................................................... .............. 38 3.4 operand address addressing........................................... ....................................................... 39 3.4.1 direct addressi ng ........................................................................................................ ................ 39 www..net
preliminary user?s manual u16898ej1v0ud 10 3.4.2 short dire ct addre ssing.................................................................................................. ..............40 3.4.3 special function r egister (sfr ) addre ssing ............................................................................... ..41 3.4.4 register addre ssing ...................................................................................................... ...............42 3.4.5 register i ndirect addr essing ............................................................................................. ...........43 3.4.6 based addressi ng......................................................................................................... ...............44 3.4.7 stack addressi ng ......................................................................................................... ................44 chapter 4 port functio ns ................................................................................................... ........45 4.1 functions of ports ............................................................................................................. ........45 4.2 port configuration ............................................................... .............................................. ........46 4.2.1 port 2......................................................................................................................... ..................47 4.2.2 port 3......................................................................................................................... ..................48 4.2.3 port 4......................................................................................................................... ..................49 4.2.4 port 12........................................................................................................................ .................54 4.2.5 port 13........................................................................................................................ .................56 4.3 registers controlling port functions ......................................................................................56 4.4 operation of port func tion ..................................................................................................... ..61 4.4.1 writing to i/o port ............................................................................................................ ............61 4.2.2 reading from i/o port .......................................................................................................... ........61 4.4.3 operations on i/o por t ......................................................................................................... ........61 chapter 5 clock generator s................................................................................................ ...62 5.1 functions of clock generators ......................................... .......................................................62 5.1.1 system clock oscilla tors....................................................................................................... ........62 5.1.2 clock oscillator for interv al time gener ation .................................................................................6 2 5.2 configuration of clock generators ..........................................................................................63 5.3 registers controlling clock generators .......................... .......................................................65 5.4 system clock oscillators ....................................................................................................... ...68 5.4.1 high-speed ring-os c oscilla tor ................................................................................................. .68 5.4.2 crystal/ceramic oscilla tor..................................................................................................... ........69 5.4.3 external clock input ci rcuit ................................................................................................... ........71 5.4.4 presca ler ...................................................................................................................... ...............71 5.5 operation of cpu clock generator ................................... .......................................................72 5.6 operation of clock generator supplying clock to peripheral hardware.............................77 chapter 6 16-bit timer/event counter 00 ................. ............................................................79 6.1 functions of 16-bit timer/event counter 00 .................... .......................................................79 6.2 configuration of 16-bit timer/event counter 00 ........ ............................................................80 6.3 registers to control 16-bit timer/event counter 00.. ............................................................84 6.4 operation of 16-bit timer/event counter 00 ................. ..........................................................90 6.4.1 interval time r operat ion ....................................................................................................... .........90 6.4.2 external event c ounter oper ation............................................................................................... ..93 6.4.3 pulse width measur ement operat ions ..........................................................................................96 6.4.4 square-wave out put operat ion................................................................................................... 104 6.4.5 ppg output operati ons .......................................................................................................... ....106 www..net
preliminary user?s manual u16898ej1v0ud 11 6.4.6 one-shot pulse out put operat ion ............................................................................................... 1 09 6.5 cautions related to 16-bit timer/event counter 00 ... ......................................................... 114 chapter 7 8-bit timer 80.................................................................................................. ............ 118 7.1 function of 8-bit timer 80........................................... .......................................................... .. 118 7.2 configuration of 8-bit timer 80 .................................. ............................................................ 11 9 7.3 register controlling 8-bit timer 80 .............................. ......................................................... 121 7.4 operation of 8-bit timer 80.................................................................................................... .122 7.4.1 operation as in terval timer .................................................................................................... .... 122 7.5 notes on 8-bit timer 80........................................................................................................ ... 124 chapter 8 8-bit timer h1 .................................................................................................. ........... 125 8.1 functions of 8-bit timer h1 ........................................... ......................................................... 125 8.2 configuration of 8-bit timer h1 .................................... ......................................................... 125 8.3 registers controlling 8-bit timer h1......................... ............................................................ 128 8.4 operation of 8-bit timer h1 .................................................................................................... 131 8.4.1 operation as interval ti mer/square-wa ve out put ........................................................................ 131 8.4.2 operation as pw m output mode ............................................................................................... 134 chapter 9 watchdog timer ................................................................................................... .... 140 9.1 functions of watchdog timer ................................................................................................ 140 9.2 configuration of watchdog timer............... ........................................................................... 142 9.3 registers controlling watchdog timer ........................ ......................................................... 143 9.4 operation of watchdog timer ........................................ ........................................................ 145 9.4.1 watchdog timer operation when ?low-speed ring- osc cannot be stopped? is selected by option byte................................................................................................................... .............. 145 9.4.2 watchdog timer operation when ?low-speed ring- osc can be stopped by software? is selected by option byte....................................................................................................... ....... 147 9.4.3 watchdog timer operation in stop mode (when ?low-speed ring-osc can be stopped by software? is se lected by opti on byte )....................................................................... 149 9.4.4 watchdog timer operation in halt mode (when ?low-speed ring-osc can be stopped by software? is se lected by opti on byte )....................................................................... 151 chapter 10 a/d converter ................................................................................................... ...... 152 10.1 functions of a/d converter ........................................... ......................................................... 1 52 10.2 configuration of a/d converter..................................... ......................................................... 155 10.3 registers used by a/d converter ................................. ......................................................... 157 10.4 a/d converter operations....................................................................................................... 162 10.4.1 basic operations of a/d conver ter ............................................................................................. 1 62 10.4.2 input voltage and conv ersion resu lts ......................................................................................... 16 4 10.4.3 a/d converter operation mode................................................................................................... 165 10.5 how to read a/d converter characteristics table ..... ......................................................... 167 10.6 cautions for a/d converter .................................................................................................... 1 69 chapter 11 serial interface uart6........................ .............................................................. 173 www..net
preliminary user?s manual u16898ej1v0ud 12 11.1 functions of serial interface uart6................................. .....................................................173 11.2 configuration of serial interf ace uart6 ...............................................................................177 11.3 registers controlling serial interface uart6 .............. ........................................................180 11.4 operation of serial interface uart6.............................. ........................................................189 11.4.1 operation stop m ode ............................................................................................................ .....189 11.4.2 asynchronous serial inte rface (uart) mode .............................................................................190 11.4.3 dedicated baud ra te gener ator .................................................................................................. 206 chapter 12 interrupt functions .................................... ........................................................2 13 12.1 interrupt function type s....................................................................................................... ..213 12.2 interrupt sources and configuratio n .....................................................................................214 12.3 interrupt function control register s.....................................................................................216 12.4 interrupt servicing oper ation .................................................................................................2 21 12.4.1 maskable interrupt request a cknowledgment operatio n.............................................................221 12.4.2 multiple interr upt serv icing ................................................................................................... ......224 12.4.3 interrupt r equest pendi ng...................................................................................................... .....225 chapter 13 standby function ................................................................................................ ..226 13.1 standby function and configuration. ....................................................................................226 13.1.1 standby f uncti on............................................................................................................... .........226 13.1.2 registers used during standby .................................................................................................. 228 13.2 standby function operatio n...................................................................................................22 9 13.2.1 halt mode ...................................................................................................................... .........229 13.2.2 stop mode...................................................................................................................... .........232 chapter 14 reset function .................................................................................................. .....236 14.1 register for confirming reset s ource...................................................................................243 chapter 15 power-on-clear circuit ............................. ........................................................244 15.1 functions of power-on-clear circui t .....................................................................................244 15.2 configuration of power-on-clear ci rcuit ...............................................................................245 15.3 operation of power-on-clear circui t......................................................................................245 15.4 cautions for power-on-clear circui t......................................................................................246 chapter 16 low-voltage detector ............................... ........................................................248 16.1 functions of low-voltage detect or .......................................................................................24 8 16.2 configuration of low-voltage detector .................................................................................248 16.3 registers controlling low-voltage detector .............. ..........................................................249 16.4 operation of low-voltage det ector........................................................................................2 51 16.5 cautions for low-voltage detector.............................. ..........................................................2 54 chapter 17 option byte...................................................................................................... ..........257 chapter 18 flash memory .................................................................................................... ......260 www..net
preliminary user?s manual u16898ej1v0ud 13 18.1 features .................................................................................................................. .................. 260 18.2 memory configuration................................................. ..................................................... ....... 261 18.3 functional outline ........................................................................................................ ........... 262 18.4 writing with flash programmer ................................. ............................................................ 264 18.5 programming environment................................................................................................... .. 266 18.6 communication mode ........................................................................................................ ..... 266 18.7 processing of pins on board............................................................................................... ... 267 18.7.1 x1 and x2 pi ns .......................................................................................................... ................ 267 18.7.2 reset pin ............................................................................................................... ................. 267 18.7.3 port pi ns ............................................................................................................... ..................... 267 18.7.4 powe r suppl y............................................................................................................ ................. 267 18.8 programming method ....................................................................................................... ....... 268 18.8.1 controlling flash me mory................................................................................................ ........... 268 18.8.2 flash memory programmi ng m ode........................................................................................... . 269 18.8.3 communica tion co mmands .................................................................................................. ..... 269 18.9 flash memory programming by self writing ........................................................................ 270 chapter 19 instruction set overview..................... ............................................................ 271 19.1 operation ................................................................................................................. ................. 271 19.1.1 operand identifiers and description methods ............................................................................ 2 71 19.1.2 description of ?operation? column....................................................................................... ...... 272 19.1.3 description of ?flag? column............................................................................................ .......... 272 19.2 operation list............................................................................................................ ............... 273 19.3 instructions listed by addressing type ................. .............................................................. 278 chapter 20 electrical specifications (target values)............................................. 281 chapter 21 package drawing ...................................... ........................................................... .293 appendix a development tools .............................................................................................. 2 94 a.1 software package ........................................................................................................... ......... 296 a.2 language processing software ..................................... ........................................................ 29 6 a.3 control software ........................................................................................................... ........... 297 a.4 flash memory writing tools................................................................................................. .. 297 a.5 debugging tools (hardware)......................................... ........................................................ .298 a.6 debugging tools (software).......................................... ....................................................... .. 299 appendix b notes on target system design................................................................... 300 appendix c register index .................................................................................................. ....... 301 c.1 register index (register name) .................................... ......................................................... 301 c.2 register index (symbol)........................................................................................................ .. 303 www..net
preliminary user?s manual u16898ej1v0ud 14 chapter 1 overview 1.1 features o minimum instruction execution ti me selectable from high speed (0.2 s) and low speed (3.2 s) (with cpu clock of 10 mhz) o general-purpose registers: 8 bits 8 registers o rom and ram capacities item part number program memory (flash memory) memory (internal high-speed ram) pd78f9221 2 kb 128 bytes pd78F9222 4 kb 256 bytes o on-chip power-on clear (poc) circuit and low voltage detector (lvi) o on-chip watchdog timer (operable on internal low-speed ring-osc clock) o i/o ports: 17 o timer: 4 channels ? 16-bit timer/event counter: 1 channel ? 8-bit timer: 2 channels ? watchdog timer: 1 channel o serial interface: uart (lin (local interconnect network) bus supported) 1 channel o 10-bit resolution a/d converter: 4 channels o supply voltage: v dd = 2.0 to 5.5 v note o operating temperature range: t a = ? 40 to +85 c note use this product in a voltage range of 2. 2 to 5.5 v because the detection voltage (v poc ) of the power-on clear (poc) circuit is 2.1 v 0.1 v. 1.2 application fields o automotive electronics ? system control of body instrum entation system (such as power wi ndows and keyless entry reception) ? sub-microcontroller of control system o household appliances ? electric toothbrushes ? electric shavers o toys o industrial equipment ? sensor and switch control ? power tools www..net
chapter 1 overview preliminary user?s manual u16898ej1v0ud 15 1.3 ordering information part number package internal rom pd78f9221mc-5a4 20-pin plastic ssop (7.62 mm (300)) flash memory pd78F9222mc-5a4 20-pin plastic ssop (7.62 mm (300)) flash memory 1.4 pin configuration (top view) 20-pin plastic ssop (7.62 mm (300)) pd78f9221mc-5a4 pd78F9222mc-5a4 v ss note p121/x1 p122/x2 p123 v dd reset/p34 p31/ti010/to00/intp2 p30/ti000/intp0 p41/intp3 18 17 16 20 19 15 14 13 12 11 av ref p20/ani0 p21/ani1 p22/ani2 p23/ani3 p130 p45 p44/rxd6 p43/txd6/intp1 p42/toh1 1 2 3 4 5 6 7 8 9 10 p40 note v ss and av ss are internally connected in the 78k 0s/ka1+. be sure to connect v ss to a stabilized gnd in order to stabilize v ss via gnd (= 0 v). ani0 to ani3: analog input reset: reset av ref : analog reference voltage rxd6: receive data rxd6: receive data ti000, ti010: timer input intp0 to intp3: external interr upt input to00, toh1: timer output p20 to p23: port 2 txd6: transmit data p30, p31, p34: port 3 v dd : power supply p40 to p45: port 4 v ss : ground p121 to p123: port 12 x1, x2: crystal oscillator (x1 input clock) p130: port 13 www..net
chapter 1 overview preliminary user?s manual u16898ej1v0ud 16 1.5 78k0s/kx1+ product lineup the following table shows the pr oduct lineup of the 78k0s/kx1+. part number item 78k0s/ku1+ 78k0s/ky1+ 78k0s/ka1+ 78k0s/kb1+ number of pins 8 pins 16 pins 20 pins 30 pins flash memory 1 kb, 2 kb, 4 kb 1 kb, 2 kb, 4 kb 2 kb 4 kb 4 kb, 8 kb internal memory ram 128 bytes 128 bytes 128 bytes 256 bytes 256 bytes supply voltage v dd = 2.0 to 5.5 v minimum instruction execution time 0.20 s (10 mhz, v dd = 4.0 to 5.5 v) 0.33 s (6 mhz, v dd = 3.0 to 5.5 v) 0.40 s (5 mhz, v dd = 2.7 to 5.5 v) 4.0 s (500 khz, v dd = 2.0 to 5.5 v) system clock (oscillation frequency) internal high-speed ring-osc oscillation (8 mhz (typ.)) crystal/ceramic oscillation (1 to 10 mhz) x1 external clock input oscillation (1 to 10 mhz) clock for tmh1 and wdt (oscillation frequency) internal low-speed ring-osc oscillation (240 khz (typ.)) cmos i/o 5 13 15 24 cmos input 1 1 1 1 port cmos output ? ? 1 1 16-bit (tm0) 1 ch 8-bit (tmh) 1 ch 8-bit (tm8) ? 1 ch timer wdt 1 ch serial interface ? lin-bus-supporting uart: 1 ch a/d converter 8 bits: 4 ch (2.7 to 5.5v) 10 bits: 4 ch (2.7 to 5.5v) external 2 4 interrupts internal 6 10 reset pin provided poc 2.1 v 0.1 v lvi provided (select able by software) reset wdt provided operating temperature range ? 40 to +85 c www..net
chapter 1 overview preliminary user?s manual u16898ej1v0ud 17 1.6 block diagram 78k0s cpu core internal high-speed ram flash memory v ss note v dd toh1/p42 port 2 p20 to p23 4 port 4 p40 to p45 6 port 13 p130 power on clear/ low voltage indicator poc/lvi control reset control port 3 p30, p31 2 p34 p121 to p123 3 port 12 system control high-speed ring-osc reset/p34 x1/p121 x2/p122 low-speed ring-osc intp0/p30 intp1/p43 intp2/p31 intp3/p41 ani0/p20 to ani3/p23 4 a/d converter av ref 8-bit timer 80 watchdog timer 8-bit timer h1 16-bit timer event counter 00 to00/ti010/p31 ti000/p30 rxd6/p44 txd6/p43 serial interface uart6 interrupt control note v ss and av ss are internally connected in the 78k 0s/ka1+. be sure to connect v ss to stabilized gnd in order to stabilize v ss via gnd (= 0 v). www..net
chapter 1 overview preliminary user?s manual u16898ej1v0ud 18 1.7 functional outline item pd78f9221 pd78F9222 flash memory 2 kb 4 kb internal memory high-speed ram 128 bytes 256 bytes memory space 64 kb x1 input clock (oscillation frequency) crystal/ceramic/external clock input: 10 mhz (v dd = 4.0 to 5.5 v), 6 mhz (v dd = 3.0 to 5.5 v), 5 mhz (v dd = 2.7 to 5.5 v), 500 khz (v dd = 2.0 to 5.5 v) high speed (oscillation frequency) internal ring oscillation: 8 mhz (typ.) ring-osc clock low speed (for tmh1 and wdt) internal ring oscillation: 240 khz (typ.) general-purpose registers 8 bits 8 registers minimum instruction execution time 0.2 s/0.8 s (x1 input clock: f x = 10 mhz) instruction set ? 16-bit operation ? bit manipulation (set, reset, test), etc. i/o port total: 17 pins cmos i/o: 15 pins cmos input: 1 pin cmos output: 1 pin timer ? 16-bit timer/event counter: 1 channel ? 8-bit timer (timer h1): 1 channel ? 8-bit timer (timer 80): 1 channel ? watchdog timer: 1 channel timer output 2 pins (pwm: 1 pin) a/d converter 10-bit resolution 4 channels serial interface lin-bus-s upporting uart mode: 1 channel external 4 vectored interrupt sources internal 10 reset ? reset by reset pin ? internal reset by watchdog timer ? internal reset by power-on clear ? internal reset by low-voltage detector supply voltage v dd = 2.0 to 5.5 v note operating temperature range ta = ? 40 to +85 c package 20-pin plastic ssop (7.62 mm (300)) note use this product in a voltage range of 2. 2 to 5.5 v because the detection voltage (v poc ) of the power-on- clear (poc) circuit is 2.1 v 0.1 v. www..net
preliminary user?s manual u16898ej1v0ud 19 chapter 2 pin functions 2.1 pin function list (1) port pins pin name i/o function after reset alternate- function pin p20 to p23 i/o port 2. 4-bit i/o port. can be set to input or output mode in 1-bit units. an on-chip pull-up resistor can be connected by setting software. input ani0 to ani3 p30 ti000/intp0 p31 i/o can be set to input or output mode in 1- bit units. an on-chip pull-up resistor can be connected by setting software. input ti010/to00/ intp2 p34 input port 3 input only input reset p40 ? p41 intp3 p42 toh1 p43 txd6/intp1 p44 rxd6 p45 i/o port 4. 6-bit i/o port. can be set to input or output mode in 1-bit units. an on-chip pull-up resistor can be connected by setting software. input ? p121 x1 p122 x2 p123 i/o port 12. 3-bit i/o port. can be set to input or output mode in 1-bit units. an on-chip pull-up resistor c an be connected only to p123 by setting software. input ? p130 output port 13. 1-bit output-only port output ? www..net
chapter 2 pin functions preliminary user?s manual u16898ej1v0ud 20 (2) non-port pins pin name i/o function after reset alternate- function pin intp0 p30/ti000 intp1 p43/txd6 intp2 p31/ti010/to00 intp3 input external interrupt input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified input p41 rxd6 input serial data input for asyn chronous serial interface input p44 txd6 output serial data output for asynch ronous serial interface input p43/intp1 ti000 external count clock input to 16-bit timer/event counter 00. capture trigger input to captur e registers (cr000 and cr010) of 16-bit timer/event counter 00 p30/intp0 ti010 input capture trigger input to captur e register (cr000) of 16-bit timer/event counter 00 input p31/to00/intp2 to00 output 16-bit timer/event counter 00 output input p31/ti010/intp2 toh1 output 8-bit timer h1 output input p42 ani0 to ani3 input analog input of a/d converter input p20 to p23 av ref ? reference voltage of a/d converter ? ? reset input system reset input ? ? x1 input connection of crystal/ceramic oscillator for system clock oscillation. external clock input ? p121 x2 ? connection of crystal/ceramic oscillator for system clock oscillation. ? p122 v dd ? positive power supply ? ? v ss ? ground potential ? ? www..net
chapter 2 pin functions preliminary user?s manual u16898ej1v0ud 21 2.2 pin functions 2.2.1 p20 to p23 (port 2) p20 to p23 constitute a 4-bit i/o port, port 2. in addition to i/o port pins, these pins also have a function to input analog signals to the a/d converter. these pins can be set to the follo wing operation modes in 1-bit units. (1) port mode p20 to p23 function as a 4-bit i/o port. each bit of th is port can be set to the i nput or output mode by using port mode register 2 (pm2). in addition, an on-chip pu ll-up resistor can be connected to the port by using pull- up resistor option register 2 (pu2). (2) control mode p20 to p23 function as the analog input pins (ani0 to ani3) of the a/d conv erter. when using these pins as analog input pins, refer to 10.6 cautions for a/d conver ter (5) ani0/p20 to ani3/p23 . 2.2.2 p30, p31, and p34 (port 3) p30, p31 and p34 constitute a 2-bit i/o port, port 3. in addi tion to i/o port pins, these pins also have functions to input/output a timer signal, and input an external interrupt request signal. p34 is a 1-bit input-only port. this pin is also used as a reset pin. p30 and p31 can be set to the following operation modes in 1-bit units. (1) port mode p30 and p31 function as a 2-bit i/o port. each bit of this port can be set to the input or output mode by using port mode register 3 (pm3). in addition, an on-chip pu ll-up resistor can be connected to the port by using pull- up resistor option register 3 (pu3). p34 functions as a 1-bit input-only port. (2) control mode p30, p31, and p34 function to input/ output signals to/from internal timers , and to input an external interrupt request signal. (a) intp0 and intp2 these are external interrupt reques t input pins for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) ti000 this pin inputs an external count clock to 16-bit timer/ event counter 00, or a capt ure trigger signal to the capture registers (cr000 and cr010) of 16-bit timer/event counter 00. (c) ti010 this pin inputs a capture trigger si gnal to the capture register (cr000) of 16-bit timer/event counter 00. (d) to00 this pin outputs a signal from 16-bit timer/event counter 00. www..net
chapter 2 pin functions preliminary user?s manual u16898ej1v0ud 22 2.2.3 p40 to p45 (port 4) p40 to p45 constitute a 6-bit i/o port, port 4. in addition to i/o port pins, these pins also have functions to output a timer signal, input external interrupt request signals, and input/output the data of the serial interface. these pins can be set to the follo wing operation modes in 1-bit units. (1) port mode p40 and p45 function as a 6-bit i/o port. each bit of this port can be set to the input or output mode by using port mode register 4 (pm4). in addition, an on-chip pu ll-up resistor can be connected to the port by using pull- up resistor option register 4 (pu4). (2) control mode p40 and 45 function to output a signal from an internal timer, input ex ternal interrupt request signals, and input/output data of t he serial interface. (a) intp1 and intp3 these are external interrupt reques t input pins for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) toh1 this is the output pin of 8-bit timer h1. (c) txd6 this pin outputs serial data from t he asynchronous serial interface. (d) rxd6 this pin inputs serial data to t he asynchronous serial interface. 2.2.4 p121 to p123 (port 12) p121 to p123 constitute a 3-bit i/o port, port 12. each bit of this port can be set to the input or output m ode by using port mode register 12 (pm12). an on-chip pull- up resistor can be connected to p123 by using pull-up resistor option register 12 (pu12). p121 and p122 also function as the x1 and x2 pins, respectively. 2.2.5 p130 (port 13) this is a 1-bit output-only port. 2.2.6 reset this pin inputs an active-low system reset signal. 2.2.7 x1 and x2 these pins connect an oscillator to oscillate the x1 input clock. supply an external clock to x1. 2.2.8 av ref this pin inputs a reference voltage to t he internal a/d converter. when the a/ d converter is not used, connect this pin to v dd . www..net
chapter 2 pin functions preliminary user?s manual u16898ej1v0ud 23 2.2.9 v dd this is the positive power supply pin. 2.2.10 v ss this is the ground pin. 2.3 pin i/o circuits and connection of unused pins table 2-1 shows i/o circuit type of eac h pin and the connections of unused pins. for the configuration of the i/o circuit of each type, refer to figure 2-1 . table 2-1. types of pin i/o circui ts and connection of unused pins pin name i/o circuit type i/o recommended connection of unused pin p20/ani0 to p23/ani3 11 p30/ti000/intp0 p31/ti010/to00/intp2 8-a i/o input: independently connect to v dd or v ss via a resistor. output: leave open. p34/reset 2 input directly connect to v dd or v ss . p40 p41/intp3 p42/toh1 p43/txd6/intp1 p44/rxd6 p45 8-a p121/x1 p122/x2 16-b p123 8-a i/o input: individually connect to v dd or v ss via resistor. output: leave open. p130 3-c output leave open. av ref ? input directly connect to v dd . www..net
chapter 2 pin functions preliminary user?s manual u16898ej1v0ud 24 figure 2-1. pin i/o circuits in v dd p-ch n-ch data out data output disable av ref p-ch n-ch in/out av ref (threshold voltage) v ss p-ch n-ch + input enable - pull up enable v dd p-ch pull up enable data output disable v dd p-ch v dd p-ch in/out n-ch p-ch feedback cut-off x1, in/out x2, in/out osc enable data output disable v dd p-ch n-ch data output disable p-ch n-ch type 2 type 3-c type 8-a type 16-b type 11 schmitt-triggered input with hysteresis characteristics comparator www..net
preliminary user?s manual u16898ej1v0ud 25 chapter 3 cpu architecture 3.1 memory space the 78k0s/ka1+ can access up to 64 kb of memory spac e. figures 3-1 and 3-2 show the memory maps. figure 3-1. memory map ( pd78f9221) special function registers (sfr) 256 8 bits internal high-speed ram 256 8 bits flash memory 4,096 8 bits program memory space data memory space program area option byte area program area callt table area vector table area use prohibited ffffh 0fffh 0000h 0080h 007fh 0082h 0081h 0040h 003fh 0022h 0021h ff00h feffh fe00h fdffh 1000h 0fffh 0000h remark the option byte is one byte at 0080h. www..net
chapter 3 cpu architecture preliminary user?s manual u16898ej1v0ud 26 figure 3-2. memory map ( pd78F9222) special function registers (sfr) 256 8 bits internal high-speed ram 256 8 bits flash memory 4,096 8 bits program memory space data memory space program area option byte area program area callt table area vector table area use prohibited ffffh 0fffh 0000h 0080h 007fh 0082h 0081h 0040h 003fh 0022h 0021h ff00h feffh fe00h fdffh 1000h 0fffh 0000h remark the option byte is one byte at 0080h. www..net
chapter 3 cpu architecture preliminary user?s manual u16898ej1v0ud 27 3.1.1 internal program memory space the internal program memory space stores programs and table data. this space is usually addressed by the program counter (pc). the 78k0s/ka1+ provides the following internal roms (or flash memory) containing the following capacities. table 3-1. internal rom capacity internal rom part number structure capacity pd78f9221 2,048 8 bits pd78F9222 flash memory 4,096 8 bits the following areas are allocated to t he internal program memory space. (1) vector table area the 34-byte area of addresses 0000h to 0021h is reserved as a vector table area. this area stores program start addresses to be used when branching by reset input or interrupt request generation. of a 16-bit address, the lower 8 bits are stored in an ev en address, and the higher 8 bits are stored in an odd address. table 3-2. vector table vector table address interrupt request vector table address interrupt request 0000h reset input 0014h intflc 0006h intlvi 0016h intp2 0008h intp0 0018h intp3 000ah inp1 001ah inttm80 000ch inttmh1 001ch intsre6 000eh inttm000 001eh intsr6 0010h inttm010 0020h intst6 0012h intad (2) callt instruction table area the subroutine entry address of a 1-byte call instruction (callt) can be stored in the 64-byte area of addresses 0040h to 007fh. (3) option byte area the option byte area is t he 1-byte area of address 0080h. for details, refer to chapter 17 option byte . 3.1.2 internal data memory space 128-byte internal high-speed ram is provided in the pd78f9221 and 256-byte in the pd78F9222. the internal high-speed ram can also be used as a stack memory. www..net
chapter 3 cpu architecture preliminary user?s manual u16898ej1v0ud 28 3.1.3 special function register (sfr) area special function registers (sfrs) of on-chip peripheral hardware are allocat ed to the area of ff00h to ffffh (see table 3-3 ). 3.1.4 data memory addressing the 78k0s/ka1+ is provided with a wide range of addressing modes to make memo ry manipulation as efficient as possible. the data memory area (fe80h to ffffh or fe00h to ffffh) can be accessed using a unique addressing mode according to its use, such as a special function register (sfr). figur es 3-3 and 3-4 illustrate the data memory addressing. figure 3-3. data memory addressing ( pd78f9221) special function registers (sfr) 256 8 bits internal high-speed ram 128 8 bits flash memory 2,048 8 bits use prohibted direct addressing register indirect addressing based addressing sfr addressing short direct addressing ffffh ff00h feffh ff20h fe1fh fe80h fe7fh 0800h 07ffh 0000h www..net
chapter 3 cpu architecture preliminary user?s manual u16898ej1v0ud 29 figure 3-4. data memory addressing ( pd78F9222) special function registers (sfr) 256 8 bits internal high-speed ram 256 8 bits flash memory 4,096 8 bits use prohibited direct addressing register indirect addressing based addressing sfr addressing short direct addressing ffffh ff00h feffh ff20h fe1fh fe00h fdffh fe20h fe1fh 1000h 0fffh 0000h www..net
chapter 3 cpu architecture preliminary user?s manual u16898ej1v0ud 30 3.2 processor registers the 78k0s/ka1+ provides the followi ng on-chip processor registers. 3.2.1 control registers the control registers have special f unctions to control the program sequenc e statuses and stack memory. the control registers include a pr ogram counter, a program stat us word, and a stack pointer. (1) program counter (pc) the program counter is a 16-bit r egister which holds the address info rmation of the next program to be executed. in normal operation, the pc is automat ically incremented according to the num ber of bytes of the instruction to be fetched. when a branch instruct ion is executed, immediate data or register contents are set. reset input sets the reset vector table values at addresses 0000h and 0001h to the program counter. figure 3-5. program counter configuration 0 15 pc14 pc15 pc pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 (2) program status word (psw) the program status word is an 8-bit r egister consisting of various flags to be set/reset by instruction execution. program status word contents ar e automatically stacked upon interr upt request generation or push psw instruction execution and ar e automatically restored upon execution of the reti and pop psw instructions. reset input sets psw to 02h. figure 3-6. program status word configuration 70 ie z 0 ac 0 0 1 cy psw (a) interrupt enable flag (ie) this flag controls interrupt request acknowledge operations of the cpu. when ie = 0, the interrupt disabled (d i) status is set. all interrupt requests except non-maskable interrupt are disabled. when ie = 1, the interrupt enabled (ei) status is set. interrupt reques t acknowledgment is controlled with an interrupt mask flag for various interrupt sources. this flag is reset to 0 upon di instruction executi on or interrupt acknowledgment and is set to 1 upon ei instruction execution. (b) zero flag (z) when the operation result is zero, this flag is set to 1. it is reset to 0 in all other cases. (c) auxiliary carry flag (ac) if the operation result has a carry from bi t 3 or a borrow at bit 3, this flag is set to 1. it is reset to 0 in all other cases. www..net
chapter 3 cpu architecture preliminary user?s manual u16898ej1v0ud 31 (d) carry flag (cy) this flag stores overflow and underfl ow that have occurred upon add/subtra ct instruction execution. it stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruct ion execution. (3) stack pointer (sp) this is a 16-bit register to hold the start address of t he memory stack area. only the internal high-speed ram area can be set as the stack area. figure 3-7. stack pointer configuration 0 15 sp14 sp15 sp sp13 sp12 sp11 sp10 sp9 sp8 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 the sp is decremented befor e writing (saving) to the stack me mory and is incremented after reading (restoring) from the stack memory. each stack operation saves/restores dat a as shown in figures 3-8 and 3-9. caution since reset input makes sp contents undefi ned, be sure to initialize the sp before instruction execution. figure 3-8. data to be saved to stack memory interrupt psw pc15 to pc8 pc15 to pc8 pc7 to pc0 lower half register pairs sp sp _ 2 sp _ 2 call, callt instructions push rp instruction sp _ 1 sp sp sp _ 2 sp _ 2 sp _ 1 sp pc7 to pc0 sp _ 3 sp _ 2 sp _ 1 sp sp sp _ 3 upper half register pairs figure 3-9. data to be restored from stack memory reti instruction psw pc15 to pc8 pc15 to pc8 pc7 to pc0 lower half register pairs ret instruction pop rp instruction sp pc7 to pc0 upper half register pairs sp + 1 sp sp + 2 sp sp + 1 sp sp + 2 sp sp + 1 sp + 2 sp sp + 3 www..net
chapter 3 cpu architecture preliminary user?s manual u16898ej1v0ud 32 3.2.2 general-purpose registers a general-purpose register consists of eight 8-bit registers (x, a, c, b, e, d, l, and h). in addition each register being used as an 8-bit register, two 8-bit registers in pairs can be used as a 16-bit register (ax, bc, de, and hl). registers can be described in terms of function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl) and absolute names (r0 to r7 and rp0 to rp3). figure 3-10. general-purpo se register configuration (a) absolute names r0 15 0 7 0 16-bit processing 8-bit processing rp3 rp2 rp1 rp0 r1 r2 r3 r4 r5 r6 r7 (b) function names x 15 0 7 0 16-bit processing 8-bit processing hl de bc ax a c b e d l h www..net
chapter 3 cpu architecture preliminary user?s manual u16898ej1v0ud 33 3.2.3 special function registers (sfrs) unlike the general-purpose register s, each special function regist er has a special function. the special function registers are alloca ted to the 256-byte area ff00h to ffffh. the special function register s can be manipulated, like t he general-purpose registers, with operation, transfer, and bit manipulation instructions. manipulatable bit units (1 , 8, and 16) differ depending on the special function register type. each manipulation bit unit can be specified as follows. ? 1-bit manipulation describes a symbol reserved by the assembler for the 1- bit manipulation instructi on operand (sfr.bit). this manipulation can also be specified with an address. ? 8-bit manipulation describes a symbol reserved by the assembler for the 8-bit manipulation instruct ion operand (sfr). this manipulation can also be specified with an address. ? 16-bit manipulation describes a symbol reserved by the assembler for the 16-bit manipulation instruct ion operand. when specifying an address, describe an even address. table 3-3 lists the special function r egisters. the meanings of the symbol s in this table are as follows: ? symbol indicates the addresses of the implem ented special function registers. t he symbols shown in this column are reserved words in the assembler, and have already been defined in a header file called ?sfrbit.h? in the c compiler. therefore, t hese symbols can be used as instruction oper ands if an assembler or integrated debugger is used. ? r/w indicates whether the special functi on register can be read or written. r/w: read/write r: read only w: write only ? number of bits manipulated simultaneously indicates the bit units (1, 8, and 16) in which the special function regi ster can be manipulated. ? after reset indicates the status of the special f unction register when a reset is input. www..net
chapter 3 cpu architecture preliminary user?s manual u16898ej1v0ud 34 table 3-3. special function registers (1/2) number of bits manipulated simultaneously address special function register (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ff02h port register 2 p2 ? ff03h port register 3 p3 ? ff04h port register 4 p4 ? ff0ch port register 12 p12 r/w note 1 ? ff0dh port register 13 p13 w ? ff0eh 8-bit timer h compare register 01 cmp01 ? ? ff0fh 8-bit timer h compare register 11 cmp11 r/w ? ? 00h ff12h ff13h 16-bit timer counter 00 tm00 r ? ? note 2 0000h ff14h ff15h 16-bit timer capture/compare register 000 cr000 ? ? note 2 0000h ff16h ff17h 16-bit timer capture/compare register 010 cr010 r/w ? ? note 2 0000h ff18h ff19h 10-bit a/d conversion result register adcr ? ? note 2 ff1ah 8-bit a/d conversion result register adcrh r ? ? undefined ff22h port mode register 2 pm2 ? ff23h port mode register 3 pm3 ? ff24h port mode register 4 pm4 ? ff2ch port mode register 12 pm12 ? ffh ff32h pull-up resistance option register 2 pu2 ? ff33h pull-up resistance option register 3 pu3 ? ff34h pull-up resistance option register 4 pu4 ? ff3ch pull-up resistance option register 12 pu12 ? 00h ff48h watchdog timer mode register wdtm ? ? 67h ff49h watchdog timer enable register wdte ? ? 9ah ff50h low voltage detect register lvim ? ? ff51h low voltage detection level select register lvis r/w ? ? 00h ff54h reset control flag register resf r ? ? 00h note 3 ff58h low-speed ring-osc mode register lsrcm ? ? ff5ah high-speed ring-osc mode register hsrcm ? ? ff60h 16-bit timer mode control register 00 tmc00 ? ff61h prescaler mode register 00 prm00 ? ff62h capture/compare control register 00 crc00 ? ff63h 16-bit timer output control register 00 toc00 ? ff70h 8-bit timer h mode register 1 tmhmd1 r/w ? 00h notes 1. only p34 is an input-only port. 2. a 16-bit access is possible only by the short direction addressing. 3. varies depending on the reset cause. www..net
chapter 3 cpu architecture preliminary user?s manual u16898ej1v0ud 35 table 3-3. special function registers (2/2) number of bits manipulated simultaneously address special function register (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ff80h a/d converter mode register adm ? ff81h analog input channel specify register ads ? ff84h port mode control register 2 pmc2 ? ff8ch input switching control register isc ? 00h ff90h asynchronous serial interface operation mode register 6 asim6 r/w ? 01h ff92h reception buffer register 6 rxb6 ? ? ffh ff93h asynchronous serial interface reception error status register 6 asis6 r ? ? 00h ff94h transmission buffer register 6 txb6 r/w ? ? ffh ff95h asynchronous serial in terface transmission status register 6 asif6 r ? ? ff96h clock selection register 6 cksr6 ? ? 00h ff97h baud rate generator control register 6 brgc6 ? ? ffh ff98h asynchronous serial interface control register 6 asicl6 ? 16h ffcch 8-bit timer mode control register 80 tmc80 r/w ? 00h ffcdh 8-bit compare register 80 cr80 w ? ? undefined ffceh 8-bit timer counter 80 tm80 r ? ? ffe0h interrupt request flag register 0 if0 ? ffe1h interrupt request flag register 1 if1 ? 00h ffe4h interrupt mask flag register 0 mk0 ? ffe5h interrupt mask flag register 1 mk1 ? ffh ffech external interrupt mode register 0 intm0 ? ? fffdh external interrupt mode register 1 intm1 ? ? 00h fff3h preprocessor clock control register ppcc ? 02h fff4h oscillation stabilization time selection register osts ? ? undefined note fffbh processor clock control register pcc r/w ? 02h note the oscillation stabilization time that elapses after release of reset is selected by the option byte. for details, refer to chapter 17 option byte . www..net
chapter 3 cpu architecture preliminary user?s manual u16898ej1v0ud 36 3.3 instruction address addressing an instruction address is determined by the program counter (p c) contents. the pc contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an in struction to be fetched each time another instruction is executed. when a branch instruction is ex ecuted, the branch destination address information is set to the pc to branch by the following addressing (for details of eac h instruction, refer to 78k/0s series instructions user?s manual (u11047e) ). 3.3.1 relative addressing [function] the value obtained by adding 8-bit immediat e data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (p c) to branch. the displacement value is treated as signed two?s complement data (?128 to +127) and bit 7 becomes the sign bit. in other words, the range of branch in relative addressing is betw een ?128 and +127 of the start address of the following instruction. this function is carried out when the br $addr16 instruct ion or a conditional branch instruction is executed. [illustration] 15 0 pc 15 0 s 15 0 pc + 876 jdisp8 when s = 0, indicates that all bits are ?0?. ... pc is the start address of the next instruction of a br instruction. when s = 1, indicates that all bits are ?1?. www..net
chapter 3 cpu architecture preliminary user?s manual u16898ej1v0ud 37 3.3.2 immediate addressing [function] immediate data in the instructi on word is transferred to the pr ogram counter (pc) to branch. this function is carried out when the call !addr 16 and br !addr16 instruct ions are executed. call !addr16 and br !addr16 instru ctions can be used to branch to all the memory spaces. [illustration] in case of call !addr16 and br !addr16 instructions 15 0 pc 87 70 call or br low addr. high addr. 3.3.3 table indirect addressing [function] the table contents (branch des tination address) of the particular locati on to be addressed by the immediate data of an instruction code from bit 1 to bit 5 are tr ansferred to the program counter (pc) to branch. table indirect addressing is carried out when the callt [addr5] inst ruction is executed. this instruction can be used to branch to all the memory spaces according to the address stored in the me mory table 40h to 7fh. [illustration] 15 1 15 0 pc 70 low addr. high addr. memory (table) effective address + 1 effective address 01 00000000 87 87 65 0 0 0 01 765 10 ta 4?0 instruction code www..net
chapter 3 cpu architecture preliminary user?s manual u16898ej1v0ud 38 3.3.4 register addressing [function] the register pair (ax) contents to be specified with an instruction word ar e transferred to the program counter (pc) to branch. this function is carried out when t he br ax instruction is executed. [illustration] 70 rp 07 ax 15 0 pc 87 www..net
chapter 3 cpu architecture preliminary user?s manual u16898ej1v0ud 39 3.4 operand address addressing the following methods (addressing) are available to s pecify the register and memo ry to undergo manipulation during instruction execution. 3.4.1 direct addressing [function] the memory indicated by immediate data in an instruction word is directly addressed. [operand format] identifier description addr16 label or 16-bit immediate data [description example] mov a, !fe00h; when setting !addr16 to fe00h instruction code 0 0 1 0 1 0 0 1 op code 0 0 0 0 0 0 0 0 00h 1 1 1 1 1 1 1 0 feh [illustration] 70 op code addr16 (low) addr16 (high) memory www..net
chapter 3 cpu architecture preliminary user?s manual u16898ej1v0ud 40 3.4.2 short direct addressing [function] the memory to be manipulated in the fixed space is dire ctly addressed with the 8-bit data in an instruction word. the fixed space where this addressing is applied is t he 256-byte space fe20h to ff1fh. an internal high- speed ram is mapped at fe20h to feffh and the specia l function registers (sfr ) are mapped at ff00h to ff1fh. the sfr area where short direct addressi ng is applied (ff00h to ff1fh) is a par t of the total sfr area. in this area, ports which are frequently access ed in a program and a compare register of the timer counter are mapped, and these sfrs can be mani pulated with a small number of bytes and clocks. when 8-bit immediate data is at 20h to ffh, bit 8 of an e ffective address is cleared to 0. when it is at 00h to 1fh, bit 8 is set to 1. see [illustration] below. [operand format] identifier description saddr label or fe20h to ff1fh immediate data saddrp label or fe20h to ff1fh i mmediate data (even address only) [description example] mov fe90h, #50h; when setting saddr to fe90h and the immediate data to 50h instruction code 1 1 1 1 0 1 0 1 op code 1 0 0 1 0 0 0 0 90h (saddr-offset) 0 1 0 1 0 0 0 0 50h (immediate data) [illustration] 15 0 short direct memory effective address 1 111111 8 0 7 op code saddr-offset when 8-bit immediate data is 20h to ffh, = 0. when 8-bit immediate data is 00h to 1fh, = 1. www..net
chapter 3 cpu architecture preliminary user?s manual u16898ej1v0ud 41 3.4.3 special function register (sfr) addressing [function] a memory-mapped special function register (sfr) is addre ssed with the 8-bit immediat e data in an instruction word. this addressing is applied to the 256-byte space ff 00h to ffffh. however, sfrs mapped at ff00h to ff1fh are accessed with short direct addressing. [operand format] identifier description sfr special function register name [description example] mov pm0, a; when selecting pm0 for sfr instruction code 1 1 1 0 0 1 1 1 0 0 1 0 0 0 0 0 [illustration] 15 0 sfr effective address 1 111111 87 0 7 op code sfr-offset 1 www..net
chapter 3 cpu architecture preliminary user?s manual u16898ej1v0ud 42 3.4.4 register addressing [function] a general-purpose register is accessed as an operand. the general-purpose register to be acce ssed is specified with t he register specify c ode and functional name in the instruction code. register addressing is carried out when an instruction with the following operand forma t is executed. when an 8-bit register is specified, one of the eight registers is specified wit h 3 bits in the instruction code. [operand format] identifier description r x, a, c, b, e, d, l, h rp ax, bc, de, hl ?r? and ?rp? can be described with absolute names (r0 to r7 and rp0 to rp3) as well as function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl). [description example] mov a, c; when selecting the c register for r instruction code 0 0 0 0 1 0 1 0 0 0 1 0 0 1 0 1 register specify code incw de; when selecting the de register pair for rp instruction code 1 0 0 0 1 0 0 0 register specify code www..net
chapter 3 cpu architecture preliminary user?s manual u16898ej1v0ud 43 3.4.5 register indirect addressing [function] the memory is addressed with the contents of the r egister pair specified as an oper and. the register pair to be accessed is specified with t he register pair specify code in the instruction code. this addressing can be carried out for all the memory spaces. [operand format] identifier description ? [de], [hl] [description example] mov a, [de]; when selecting register pair [de] instruction code 0 0 1 0 1 0 1 1 [illustration] 15 0 8 d 7 e 0 7 7 0 a de the contents of addressed memory are transferred memory address specified by register pair de www..net
chapter 3 cpu architecture preliminary user?s manual u16898ej1v0ud 44 3.4.6 based addressing [function] 8-bit immediate data is added to the cont ents of the base register, that is, t he hl register pair, and the sum is used to address the memory. addition is performed by ex panding the offset data as a pos itive number to 16 bits. a carry from the 16th bit is ignored. this addre ssing can be carried out for all the memory spaces. [operand format] identifier description ? [hl+byte] [description example] mov a, [hl+10h]; when setting byte to 10h instruction code 0 0 1 0 1 1 0 1 0 0 0 1 0 0 0 0 3.4.7 stack addressing [function] the stack area is indirectly addressed with the stack pointer (sp) contents. this addressing method is automatically employed when the push, pop, subrout ine call, and return instructions are executed or the register is sav ed/restored upon interrupt request generation. stack addressing can be used to access t he internal high-speed ram area only. [description example] in the case of push de instruction code 1 0 1 0 1 0 1 0 www..net
preliminary user?s manual u16898ej1v0ud 45 chapter 4 port functions 4.1 functions of ports the 78k0s/ka1+ has the ports shown in figure 4-1, which can be used for various control operations. table 4-1 shows the functions of each port. in addition to digital i/o port function s, each of these ports has an alter nate function. for details, refer to chapter 2 pin functions . figure 4-1. port functions p45 port 4 p20 port 2 p23 p30 p31 port 3 p40 port 13 p130 p34 p121 p123 port 12 www..net
chapter 4 port functions preliminary user?s manual u16898ej1v0ud 46 table 4-1. port functions pin name i/o function after reset alternate- function pin p20 to p23 i/o port 2. 4-bit i/o port. can be set to input or output mode in 1-bit units. on-chip pull-up resistor can be connected by setting software. input ani0 to ani3 p30 ti000/intp0 p31 i/o can be set to input or output mode in 1- bit units. on-chip pull-up resistor can be connected by setting software. input ti010/to00/ intp2 p34 input port 3 input only input reset p40 ? p41 intp3 p42 toh1 p43 txd6/intp1 p44 rxd6 p45 i/o port 4. 6-bit i/o port. can be set to input or output mode in 1-bit units. on-chip pull-up resistor can be connected setting software. input ? p121 x1 p122 x2 p123 i/o port 12. 3-bit i/o port. can be set to input or output mode in 1-bit units. on-chip pull-up resistor can be connected only to p123 by setting software. input ? p130 output port 13. 1-bit output-only port. output ? remarks 1. p121 and p122 can be allocated when the high- speed ring-osc is selected as the system clock. 2. p121 can be allocated when an external clock is selected as the system clock. 4.2 port configuration ports consist of the following hardware units. table 4-2. configuration of ports item configuration control registers port mode registers (pm2, pm3, pm4, pm12) port mode control register 2 (pmc2) port registers (p2, p3, p4, p12, p13) pull-up resistor option registers (pu2, pu3, pu4, pu12) ports total: 17 (cmos i/o: 15, cmos input: 1, cmos output: 1) pull-up resistor total: 13 www..net
chapter 4 port functions preliminary user?s manual u16898ej1v0ud 47 4.2.1 port 2 port 2 is a 4-bit i/o port with an output latch. each bit of this port ca n be set to the input or output mode by using port mode register 2 (pm2). when the p20 to p23 pins ar e used as an input port, an on-chip pull-up resistor can be connected in 1-bit units by using pull- up resistor option register 2 (pu2). this port is also used as the analog input pins of the internal a/d converter. reset input sets port 2 to the input mode. figure 4-2 shows the block diagram of port 2. figure 4-2. block diagram of p20 to p23 p20/ani0 to p23/ani3 wr pu rd pu20 to pu23 wr pm pm20 to pm23 v dd p-ch pu2 pmc2 pm2 wr port output latch (p20 to p23) pmc20 to pmc23 a/d converter internal bus selector pu2: pull-up resistor option register 2 pm2: port mode register 2 pmc2: port mode control register 2 rd: read signal wr : write signal www..net
chapter 4 port functions preliminary user?s manual u16898ej1v0ud 48 4.2.2 port 3 pins p30 and p31 constitute a 2-bit i/o por t with an output latch. each bit of this port can be set to the input or output mode by using port mode register 3 (pm3). when t he p30 to p31 pins are used as an input port, an on-chip pull-up resistor can be connected in 1-bit units by using pull-up resistor option register 3 (pu3). this port is also used as external interrupt request input pins. the p34 pin is a 1-bit input-only port and fu nctions alternately as the reset pin. reset input sets port 3 to the input mode. figures 4-3 and 4-4 show the block diagrams of port 3. caution because the p34 pin functions al ternately as the reset pin, if it is used as an input port pin, the function to input an external reset signal to the reset pin cannot be used. the function of the port is selected by the option byte. for details, refer to chapter 17 option byte. if a low level is input to the r eset pin before the option byte is referenced again after reset is released by the poc circuit, the 78k0s/ka1+ is reset and is held in the reset state until a high level is input to the reset pin. figure 4-3. block diagram of p30 and p31 p30/ti000/intp0, p31/ti010/to00/intp2 wr pu rd wr port wr pm pu30, pu31 alternate function output latch (p30, p31) pm30, pm31 alternate function v dd p-ch pu3 pm3 internal bus selector pu3: pull-up resistor option register 3 pm3: port mode register 3 rd: read signal wr : write signal www..net
chapter 4 port functions preliminary user?s manual u16898ej1v0ud 49 figure 4-4. block diagram of p34 rd p34/reset option byte reset internal bus rd: read signal 4.2.3 port 4 port 4 is a 6-bit i/o port with an output latch. each bit of this port can be set to the input or output mode by using port mode register 4 (pm4). when the p40 to p45 pins ar e used as an input port, an on-chip pull-up resistor can be connected in 1-bit units by using pull- up resistor option register 4 (pu4). alternate functions include exter nal interrupt request input, serial interface data i/o, and timer output. reset input sets port 4 to the input mode. figures 4-5 to 4-8 show the block diagrams of port 4. www..net
chapter 4 port functions preliminary user?s manual u16898ej1v0ud 50 figure 4-5. block diagram of p40 and p45 p40, p45 wr pu rd wr port wr pm pu40, pu45 output latch (p40, p45) pm40, pm45 v dd p-ch pu4 pm4 internal bus selector pu4: pull-up resistor option register 4 pm4: port mode register 4 rd: read signal wr : write signal www..net
chapter 4 port functions preliminary user?s manual u16898ej1v0ud 51 figure 4-6. block diagram of p41 and p44 p41/intp3, p44/rxd6 wr pu rd wr port wr pm pu41, pu44 alternate function output latch (p41, p44) pm41, pm44 v dd p-ch pu4 pm4 internal bus selector pu4: pull-up resistor option register 4 pm4: port mode register 4 rd: read signal wr : write signal www..net
chapter 4 port functions preliminary user?s manual u16898ej1v0ud 52 figure 4-7. block diagram of p42 p42/toh1 wr pu rd wr port wr pm pu42 output latch (p42) pm42 alternate function v dd p-ch pm4 pu4 internal bus selector pu4: pull-up resistor option register 4 pm4: port mode register 4 rd: read signal wr : write signal www..net
chapter 4 port functions preliminary user?s manual u16898ej1v0ud 53 figure 4-8. block diagram of p43 p43/tx6/intp1 wr pu rd wr port wr pm pu43 alternate function alternate function output latch (p43) pm43 v dd p-ch pu4 pm4 internal bus selector pu4: pull-up resistor option register 4 pm4: port mode register 4 rd: read signal wr : write signal www..net
chapter 4 port functions preliminary user?s manual u16898ej1v0ud 54 4.2.4 port 12 port 12 is a 3-bit i/o port with an output latch. each bit of th is port can be set to the in put or output mode by using port mode register 12 (pm12). when the p123 pin is us ed as an input port, an on-chip pull-up resistor can be connected by using pull-up resist or option register 12 (pu12). reset input sets port 12 to the input mode. the p121 and p122 pins are also used as the x1 and x2 pins of the system clock oscillator. the functions of the p121 and p122 pins differ, therefore, depending on the selected system clock os cillator. the following three system clock oscillators can be used. (1) high-speed ring-osc circuit the p121 and p122 pins can be used as i/o port pins. (2) crystal/ceram ic oscillator the p121 and p122 pins cannot be used as i/o port pi ns because they are used as the x1 and x2 pins. (3) external clock input the p121 pin is used as the x1 pin to input an external clock, and therefore it cannot be used as an i/o port pin. the p122 pin can be used as an i/o port pin. the system clock oscillation is selected by the option byte. for details, refer to chapter 17 option byte . figures 4-9 to 4-10 show the block diagrams of port 12. figure 4-9. block diagram of p121 and p122 p121/x1, p122/x2 rd wr port wr pm output latch (p121, p122) pm121, pm122 pm12 clock input internal bus selector pm12: port mode register 12 rd: read signal wr : write signal www..net
chapter 4 port functions preliminary user?s manual u16898ej1v0ud 55 figure 4-10. blo ck diagram of p123 p123 wr pu rd wr port wr pm pu123 output latch (p123) pm123 v dd p-ch pm12 pu12 internal bus selector pu12: pull-up resistor option register 12 pm12: port mode register 12 rd: read signal wr : write signal www..net
chapter 4 port functions preliminary user?s manual u16898ej1v0ud 56 4.2.5 port 13 this is a 1-bit output-only port. figure 4-11 shows the block diagram of port 13. figure 4-11. blo ck diagram of p130 rd output latch (p130) wr port p130 internal bus rd: read signal wr : write signal remark when a reset is input, p130 outputs a low level. if p130 outputs a high level immediately after reset is released, the output signal of p130 can be used as a dummy cpu reset signal. 4.3 registers controlling port functions the ports are controlled by the follo wing four types of registers. ? port mode registers (pm2, pm3, pm4, pm12) ? port registers (p2, p3, p4, p12, p13) ? port mode control register 2 (pmc2) ? pull-up resistor option registers (pu2, pu3, pu4, pu12) (1) port mode registers (pm2, pm3, pm4, pm12) these registers are used to set the corresponding port to the input or output mode in 1-bit units. each port mode register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets these registers to ffh. when a port pin is used as an alternate-function pin, se t its port mode register and output latch as shown in table 4-3. caution because p30, p31, and p4 3 are also used as external in terrupt pins, the corresponding interrupt request flag is set if each of these pins is set to the output mode and its output level is changed. to use the port pin in the output mode, therefore, set the corresponding interrupt mask flag to 1 in advance. www..net
chapter 4 port functions preliminary user?s manual u16898ej1v0ud 57 figure 4-12. format of port mode register address: ff22h, after reset: ffh, r/w symbol 7 6 5 4 3 2 1 0 pm2 1 1 1 1 pm23 pm22 pm21 pm20 address: ff23h, after reset: ffh, r/w symbol 7 6 5 4 3 2 1 0 pm3 1 1 1 1 1 1 pm31 pm30 address: ff24h, after reset: ffh, r/w symbol 7 6 5 4 3 2 1 0 pm4 1 1 pm45 pm44 pm43 pm42 pm41 pm40 address: ff2ch, after reset: ffh, r/w symbol 7 6 5 4 3 2 1 0 pm12 1 1 1 1 pm123 pm122 pm121 1 pmmn selection of i/o mode of pmn pin (m = 2, 3, 4, or 12; n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) (2) port registers (p2, p3, p4, p12, p13) these registers are used to write dat a to be output from the corresponding port pin to an external device connected to the chip. when a port register is read, the pin level is read in t he input mode, and the value of the output latch of the port is read in the output mode. p20 to p23, p30, p31, p34, p40 to p45, p121 to p1 23, and p130 are set by using a 1-bit or 8-bit memory manipulation instruction. reset input sets these registers to 00h. www..net
chapter 4 port functions preliminary user?s manual u16898ej1v0ud 58 figure 4-13. format of port register address: ff02h, after reset: 00h (output latch) r/w symbol 7 6 5 4 3 2 1 0 p2 0 0 0 0 p23 p22 p21 p20 address: ff03h, after reset: 00h note (output latch) r/w note symbol 7 6 5 4 3 2 1 0 p3 0 0 0 p34 0 0 p31 p30 address: ff04h, after reset: 00h (output latch) r/w symbol 7 6 5 4 3 2 1 0 p4 0 0 p45 p44 p43 p42 p41 p40 address: ff0ch, after reset: 00h (output latch) r/w symbol 7 6 5 4 3 2 1 0 p12 0 0 0 0 p123 p122 p121 0 address: ff0dh, after reset: 00h (output latch) r/w symbol 7 6 5 4 3 2 1 0 p13 0 0 0 0 0 0 0 p130 m = 2, 3, 4, 12, or 13; n = 0-7 pmn controls of output data (in output mode) input data read (in input mode) 0 output 0 input low level 1 output 1 input high level note because p34 is read-only, its reset value is undefined. (3) port mode control register 2 (pmc2) this register specifies the port mode or alte rnate function (a/d converter) of port 2. each bit of the pmc2 register corresponds to eac h pin of port 2 and can be specified in 1-bit units. pmc2 is set by using a 1-bit or 8-bit memory manipulation instruction. reset input sets pmc2 to 00h. www..net
chapter 4 port functions preliminary user?s manual u16898ej1v0ud 59 figure 4-14. format of port mode control register 2 address: ff84 h, after reset: r/w symbol 7 6 5 4 3 2 1 0 pmc2 0 0 0 0 pmc23 pmc22 pmc21 pmc20 pmc2n specification of operation mode (n = 0 to 3) 0 port mode 1 alternate-function mode (a/d converter) table 4-3. setting of port mode register, port regi ster (output latch), and port mode control register when alternate function is used alternate-function pin pin name name i/o pm p pmc2n (n = 0 to 3) p20 to p23 ani0 to ani3 input 1 1 ti000 input 1 ? p30 intp0 input 1 ? to00 output 0 0 ? ti010 input 1 ? p31 intp2 input 1 ? p41 intp3 input 1 ? p42 toh1 output 0 0 ? txd6 output 0 1 ? p43 intp1 input 1 ? p44 rxd6 input 1 ? remark : don?t care pm : port mode register, p : port register (output latch of port) pmc2 : port mode control register www..net
chapter 4 port functions preliminary user?s manual u16898ej1v0ud 60 (4) pull-up resistor option re gisters (pu2, pu3, pu4, pu12) these registers are used to specify w hether an on-chip pull-up resistor is c onnected to p20 to p23, p30, p31, p40 to p45, and p123. by setting pu2, pu3, pu4, or pu12, an on-chip pull-up resistor can be connected to the port pin corresponding to the bi t of pu2, pu3, pu4, or pu12. pu2, pu3, pu4, and pu12 are set by using a 1-bi t or 8-bit memory manipulation instruction. reset input set these registers to 00h. figure 4-15. format of pull-up resistor option register address: ff32 h, after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 pu2 0 0 0 0 pu23 pu22 pu21 pu20 address: ff33 h, after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 pu3 0 0 0 0 0 0 pu31 pu30 address: ff34 h, after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 pu4 0 0 pu45 pu44 pu43 pu42 pu41 pu40 address: ff3c h, after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 pu12 0 0 0 0 pu123 0 0 0 pumn selection of connection of on-chip pull-up resistor of pmn (m = 2, 3, 4, or 12; n = 0 to 7) 0 does not connect on-chip pull-up resistor 1 connects on-chip pull-up resistor www..net
chapter 4 port functions preliminary user?s manual u16898ej1v0ud 61 4.4 operation of port function the operation of a port differs, as follows , depending on the setting of the i/o mode. caution although a 1-bit memory ma nipulation instruction manipulates 1 bit, it accesses a port in 8-bit units. therefore, the contents of the output latch of a pin in the input mode, even if it is not subject to manipulation by the instruction, are undefined in a port with a mixture of inputs and outputs. 4.4.1 writing to i/o port (1) in output mode a value can be written to the output latc h by a transfer instruction. in additi on, the contents of the output latch are output from the pin. once data is wri tten to the output latch, it is retained until new data is written to the output latch. reset input cleans the data in the output latch. (2) in input mode a value can be written to t he output latch by a transfer instruction. because the output buffer is off, however, the pin status remains unchanged. once data is written to the output latch, it is re tained until new data is wri tten to the output latch. 4.4.2 reading from i/o port (1) in output mode the contents of the output latc h can be read by a transfer instruction. the contents of the output latch remain unchanged. (2) in input mode the pin status can be read by a transfe r instruction. the contents of t he output latch remain unchanged. 4.4.3 operations on i/o port (1) in output mode an operation is performed on the contents of the output latc h and the result is written to the output latch. the contents of the output latch are output from the pin. once data is written to the output latch, it is re tained until new data is wri tten to the output latch. reset input clears the dat a in the output latch. (2) in input mode the pin level is read and an operation is performed on its c ontents. the operation result is written to the output latch. however, the pin status remain s unchanged becaus e the output buffer is off. www..net
preliminary user?s manual u16898ej1v0ud 62 chapter 5 clock generators 5.1 functions of clock generators the clock generators include a circuit that generates a clock (system clock) to be supplied to the cpu and peripheral hardware, and a circuit that generates a clock (interval time gen eration clock) to be supplied to the watchdog timer and 8-bit timer h1 (tmh1). 5.1.1 system clock oscillators the following three types of system clock oscillators are used. ? high-speed ring-osc oscillator this circuit internally oscillates a cl ock of 8 mhz (typ.). its oscillation ca n be stopped by execution of the stop instruction. if the high-speed ring-osc oscillator is selected to supply the system clock, the x1 an d x2 pins can be used as i/o port pins. ? crystal/ceramic oscillator this circuit oscillates a clock with a crystal/ceramic oscillator connected across the x1 and x2 pins. it can oscillate a clock of 500 khz to 10 mhz. oscillation of this circuit can be stopped by execution of the stop instruction. ? external clock input circuit this circuit supplies a clock from an external ic to the x1 pin. a clock of 500 khz to 10 mhz can be supplied. internal clock supply can be stopped by execution of the stop instruction. if the external clock input is selected as the syst em clock, the x2 pin can be used as an i/o port pin. the system clock source is se lected by using the option byte. for details, refer to chapter 17 option byte . when using the x1 and x2 pins as i/o port pins, refer to chapter 4 port functions for details. 5.1.2 clock oscillator fo r interval time generation the following circuit is used as a clock oscillator for interval time generation. ? low-speed ring-osc oscillator this circuit oscillates a clock of 240 khz (typ.). its oscillation can be stopped by using the low-speed ring-osc mode register (lsrcm) when it is spec ified by the option byte that its o scillation can be stopped by software. www..net
chapter 5 clock generators preliminary user?s manual u16898ej1v0ud 63 5.2 configuration of clock generators the clock generators consist of the following hardware. table 5-1. configuration of clock generators item configuration control registers processor clock control register (pcc) preprocessor clock control register (ppcc) low-speed ring-osc mode register (lsrcm) high-speed ring-osc mode register (hsrcm) oscillation stabilization time select register (osts) oscillators crystal/ceramic oscillator high-speed ring-osc oscillator external clock input circuit low-speed ring-osc oscillator www..net
chapter 5 clock generators preliminary user?s manual u16898ej1v0ud 64 figure 5-1. block diagra m of clock generators x1/p121 x2/p122 f x f x 2 pcc1 controller selector cpu clock (f cpu ) internal bus internal bus oscillation stabilization time select register (osts) preprocessor clock control register (ppcc) processor clock control register (pcc) hsrstop stop ppcc1 ppcc0 osts1 osts0 f xp 2 2 f xp f x 2 2 f rl lsrstop f rh cpu system clock oscillation stabilization time counter selector prescaler clock to peripheral hardware (f xp ) 8-bit timer h1, watchdog timer option byte 1: cannot be stopped. 0: can be stopped. low-speed ring-osc mode register (lsrcm) high-speed ring-osc mode register (hsrcm) high-speed ring-osc is selected as system clock source clock for flash memory self programming control low-speed ring-osc oscillator prescaler system clock oscillator note external clock input crystal/ceramic oscillation high-speed ring-osc oscillation note select the high-speed ring-osc oscillator, crystal/cer amic oscillator, or external clock input as the system clock source by using the option byte. www..net
chapter 5 clock generators preliminary user?s manual u16898ej1v0ud 65 5.3 registers controlling clock generators the clock generators are controlled by the following five registers. ? processor clock control register (pcc) ? preprocessor clock control register (ppcc) ? low-speed ring-osc mode register (lsrcm) ? high-speed ring-osc mode register (hsrcm) ? oscillation stabilization time select register (osts) (1) processor clock control register (pcc) and pre-processor clock control register (ppcc) these registers are used to specify t he division ratio of the system clock. pcc and ppcc are set by using a 1-bit or 8-bit memory manipulation instruction. reset input sets pcc and ppcc to 02h. figure 5-2. format of processor clock control register (pcc) address: fffbh, after reset: 02h, r/w symbol 7 6 5 4 3 2 1 0 pcc 0 0 0 0 0 0 pcc1 0 figure 5-3. format of preprocesso r clock control register (ppcc) address: fff3h, after reset: 02h, r/w symbol 7 6 5 4 3 2 1 0 ppcc 0 0 0 0 0 0 ppcc1 ppcc0 ppcc1 ppcc0 pcc1 selection of cpu clock (f cpu ) 0 0 0 f x 0 1 0 f x /2 note 1 0 0 1 f x /2 2 1 0 0 f x /2 2 note 2 0 1 1 f x /2 3 note 1 1 0 1 f x /2 4 note 2 other than above setting prohibited notes 1. if ppcc = 01h, the clock (f xp ) supplied to the peripheral hardware is f x /2. 2. if ppcc = 02h, the clock (f xp ) supplied to the peripheral hardware is f x /2 2 . www..net
chapter 5 clock generators preliminary user?s manual u16898ej1v0ud 66 the fastest instruction of t he 78k0s/ka1+ is executed in two cpu clocks. therefore, the relationship between the cpu clock (f cpu ) and the minimum instruction execution time is as shown in table 5-2. table 5-2. relationship between cpu clo ck and minimum instruction execution time minimum instruction execution time: 2/f cpu cpu clock (f cpu ) note high-speed ring-osc clock (at 8.0 mhz (typ.)) crystal/ceramic oscillation clock or external clock input (at 10.0 mhz) f x 0.25 s 0.2 s f x /2 0.5 s 0.4 s f x /2 2 1.0 s 0.8 s f x /2 3 2.0 s 1.6 s f x /2 4 4.0 s 3.2 s note the cpu clock (high-speed ring-osc clock, crystal/ceram ic oscillation clock, or external clock input) is selected by the option byte. (2) low-speed ring-osc mode register (lsrcm) this register is used to select the operation mode of t he low-speed ring-osc oscillator (240 khz (typ.)). this register is valid when it is specified by the opt ion byte that the low-speed ring-osc oscillator can be stopped by software. if it is spec ified by the option byte that the low-speed ring-osc oscillator cannot be stopped by software, setting of this register is in valid, and the low-speed ring-osc oscillator continues oscillating. in addition, the source clock of wdt is fix ed to the low-speed ring-osc oscillator. for details, refer to chapter 9 watchdog timer . lsrcm can be set by using an 8-bit memory manipulation instruction. reset input sets lsrcm to 00h. figure 5-4. format of low-speed ring-osc mode register (lsrcm) address: ff58h, after reset: 00h, r/w symbol 7 6 5 4 3 2 1 0 lsrcm 0 0 0 0 0 0 0 lsrstop lsrstop oscillation/stop of low-speed ring-osc 0 low-speed ring-osc oscillates 1 low-speed ring-osc stops (3) high-speed ring-osc mode register (hsrcm) this register is used to select the operation mode of the high-speed ring-osc oscillator that generates a clock (8 mhz (typ.)) for controlling self programming of the flash memory. this register is valid when crystal/ceramic oscillation or external clock input is selected as the system clock source by the option byte. setting of this register is invalid when the high-speed ring-osc oscillator is selected by the option byte. www..net
chapter 5 clock generators preliminary user?s manual u16898ej1v0ud 67 if crystal/ceramic oscillation or external clock input is selected as the system clock source, the high-speed ring- osc oscillator must be oscillated during self-programming of the flash memory. while self-programming is not executed, stop oscillation of the high-speed ring-osc os cillator to reduce the current consumption. for self- programming of the flash memory, refer to chapter 18 flash memory . hsrcm is set by using an 8-bit memory manipulation instruction. reset input sets hsrcm to 00h. figure 5-5. format of high-speed ring-osc mode register (hsrcm) address: ff5ah, after reset: 00h, r/w symbol 7 6 5 4 3 2 1 0 hsrcm 0 0 0 0 0 0 0 hsrstop hsrstop oscillation/stops of high-speed ring-osc 0 high-speed ring-osc oscillates 1 high-speed ring-osc oscillates stops (4) oscillation stabilization time select register (osts) this register is used to select oscill ation stabilization time of the clock su pplied from the oscillator when the stop mode is released. the wait time set by osts is valid on ly when the crystal/ceramic oscillation clock is selected as the system clock and after the stop mode is released. if the high-speed ring-osc oscillator or external clock input is selected as the system clock source, no wait time elapses. the system clock oscillator and the oscill ation stabilization time that elapses after power application or release of reset are selected by the option byte. for details, refer to chapter 17 option byte . osts is set by using an 8-bit me mory manipulation instruction. figure 5-6. format of oscillation stabiliz ation time select register (osts) address: fff4h, after reset: undefined, r/w symbol 7 6 5 4 3 2 1 0 osts 0 0 0 0 0 0 osts1 osts0 osts1 osts0 selection of oscillation stabilization time 0 0 2 10 /f x 102.4 s 0 1 2 12 /f x 409.6 s 1 0 2 15 /f x 3.27 ms 1 1 2 17 /f x 13.1 ms cautions 1. to set and then release the stop mode , set the oscillation stabil ization time as follows. expected oscillation stab ilization time of resonator oscillation stabilization time set by osts 2. the wait time after the st op mode is released does not incl ude the time from the release of the stop mode to the start of clock oscilla tion (?a? in the figure below), regardless of whether stop mode was released by reset input or inte rrupt generation. www..net
chapter 5 clock generators preliminary user?s manual u16898ej1v0ud 68 stop mode is released voltage waveform of x1 pin a caution 3. the oscillation stabilizatio n time that elapses on power applicat ion or after release of reset is selected by the option byte . for details, refer to chapter 17 option byte. remarks 1. ( ): f x = 10 mhz 2. determine the oscillation stabilization time of t he resonator by checking the characteristics of the resonator to be used. 5.4 system clock oscillators the following three types of system clock oscillators are available. ? high-speed ring-osc oscillator: internal ly oscillates a clock of 8 mhz (typ.). ? crystal/ceramic oscillator: oscillates a clock of 500 khz to 10 mhz. ? external clock input circuit: supplies a clock of 500 khz to 10 mhz to the x1 pin. 5.4.1 high-speed ri ng-osc oscillator the 78k0s/ka1+ includes a high-speed ring-osc oscillator (8 mhz (typ.)). if the high-speed ring-osc is selected by the option byte as the clock source, the x1 and x2 pins can be used as i/o port pins. for details of the option byte, refer to chapter 17 option byte . for details of i/o ports, refer to chapter 4 port functions . www..net
chapter 5 clock generators preliminary user?s manual u16898ej1v0ud 69 5.4.2 crystal/ceram ic oscillator the crystal/ceramic oscillator oscill ates using a crystal or ceramic resonator connected between the x1 and x2 pins. if the crystal/ceramic oscillator is sele cted by the option byte as the system clock source, the x1 and x2 pins are used as crystal or ceramic resonator connection pins. for details of the option byte, refer to chapter 17 option byte . for details of i/o ports, refer to chapter 4 port functions . figure 5-7 shows the external circuit of the crystal/ceramic oscillator. figure 5-7. external circuit of crystal/ceramic oscillator v ss x1 x2 crystal resonator or ceramic resonator caution when using the crystal/ceram ic oscillator, wire as follows in the area enclosed by the broken lines in figure 5-7 to avoid an ad verse effect from wiring capacitance. ? keep the wiring length as short as possible. do not cross the wiring with the other signal lin es. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the osc illator capacitor the sa me potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. www..net
chapter 5 clock generators preliminary user?s manual u16898ej1v0ud 70 figure 5-8 shows examples of incorrect resonator connection. figure 5-8. examples of incorre ct resonator connection (1/2) (a) too long wiring of connected circuit (b) crossed signal lines v ss x1 x2 v ss x1 x2 port (c) wiring near high fluctuating current (d) current flowing through ground line of oscillator (potential at points a, b, and c fluctuates.) v ss x1 x2 high current v ss x1 x2 port v dd ab c high current www..net
chapter 5 clock generators preliminary user?s manual u16898ej1v0ud 71 figure 5-8. examples of incorre ct resonator connection (2/2) (e) signals are fetched v ss x1 x2 5.4.3 external clock input circuit this circuit supplies a clock from an external ic to the x1 pin. if external clock input is selected by the option byte as the system clock source, the x2 pin can be used as an i/o port pin. for details of the option byte, refer to chapter 17 option byte . for details of i/o ports, refer to chapter 4 port functions . figure 5-9 shows an external circuit of the external clock input circuit. figure 5-9. external circuit of external clock input circuit x1 external clock 5.4.4 prescaler the prescaler divides the clock (f x ) output by the system clock osc illator to gener ate a clock (f xp ) to be supplied to the peripheral hardware. it also divides the clock to peripheral hardware (f xp ) to generate a clock to be supplied to the cpu. remark the clock output by the oscillator selected by the option byte (high-speed ring-osc oscillator, crystal/ceramic oscillator, or external clock input circui t) is divided. for details of the option byte, refer to chapter 17 option byte . www..net
chapter 5 clock generators preliminary user?s manual u16898ej1v0ud 72 5.5 operation of cpu clock generator a clock (f cpu ) is supplied to the cpu from the system clock (f x ) oscillated by one of the following three types of oscillators. ? high-speed ring-osc oscillator: internal ly oscillates a clock of 8 mhz (typ.). ? crystal/ceramic oscillator: oscillates a clock of 500 khz to 10 mhz. ? external clock input circuit: supplies a clock of 500 khz to 10 mhz to x1 pin. the system clock oscillator is sele cted by the option byte. for deta ils of the option byte, refer to chapter 17 option byte . (1) high-speed ring-osc oscillator when the high-speed ring-osc oscillator is selected by the option byte, the following is possible. ? shortening of start time if the high-speed ring-osc oscillator is selected as t he oscillator, the cpu can be started without having to wait for the oscillation stabilization time of the system clock. therefore, the st art time can be shortened. ? improvement of expandability if the high-speed ring-osc oscillator is selected as the oscillator, the x1 and x2 pins can be used as i/o port pins. for details, refer to chapter 4 port functions . figures 5-10 and 5-11 show the timing chart and status transition diagram of the def ault start by the high-speed ring-osc oscillator. remark when the high-speed ring-osc oscillat or is used, the clock accuracy is 5%. figure 5-10. timing chart of default start by high-speed ring-osc oscillator v dd high-speed ring-osc clock pcc = 02h, ppcc = 02h (a) (b) h reset internal reset system clock cpu clock option byte is read. system clock is selected. (operation stops: 8/f rl + 96/f rh ) remark f rl : low-speed ring-osc clock oscillation frequency f rh : high-speed ring-osc clock oscillation frequency www..net
chapter 5 clock generators preliminary user?s manual u16898ej1v0ud 73 (a) the internal reset signal is generated by the power-on clear function on power application, the option byte is referenced after reset, and the system clock is selected. (b) the option byte is referenced and the system clo ck is selected. then the high-speed ring-osc clock operates as the system clock. figure 5-11. status transition of default start by high-speed ring-osc halt instruction stop instruction v dd > 2.1 v 0.1 v start with pcc = 02h, ppcc = 02h halt stop interrupt reset signal interrupt power application reset by power-on clear high-speed ring-osc selected by option byte clock division ratio variable during cpu operation remark pcc: processor clock control register ppcc: preprocessor clock control register (2) crystal/ceram ic oscillator if crystal/ceramic oscillation is se lected by the option byte, a clock frequency of 500 khz to 10 mhz can be selected and the accuracy of processing is improved becau se the frequency deviation is small, as compared with high-speed ring-osc oscillation (8 mhz (typ.)). figures 5-12 and 5-13 show the timing chart and status transition diagram of default st art by the crystal/ceramic oscillator. www..net
chapter 5 clock generators preliminary user?s manual u16898ej1v0ud 74 figure 5-12. timing chart of default start by crystal/ceramic oscillator v dd crystal/ceramic oscillator clock pcc = 02h, ppcc = 02h (a) (b) (c) h reset system clock internal reset cpu clock option byte is read. system clock is selected. (operation stops: 8/f rl + 96/f rh ) clock oscillation stabilization time note note the clock oscillation stabilization time for default star t is selected by the option byte. for details, refer to chapter 17 option byte . the oscillation stabilization time that elapses after the stop mode is released is selected by the oscillation stab ilization time select register (osts). remark f rl : low-speed ring-osc clock oscillation frequency f rh : high-speed ring-osc clock oscillation frequency (a) the internal reset signal is generated by the power- on clear function on power application, the option byte is referenced after reset, and the system clock is selected. (b) after high-speed ring-osc clock is generated, th e option byte is referenc ed and the system clock is selected. in this case, the crystal/ceramic os cillator clock is selected as the system clock. (c) if the system clock is the crystal/ceramic oscillator clock, it starts operating as the cpu clock after clock oscillation is stabilized. the wait time is selected by the option byte. for details, refer to chapter 17 option byte . www..net
chapter 5 clock generators preliminary user?s manual u16898ej1v0ud 75 figure 5-13. status transition of defa ult start by crysta l/ceramic oscillation halt stop halt instruction stop instruction v dd > 2.1 v 0.1 v start with pcc = 02h, ppcc = 02h interrupt reset signal interrupt power application clock division ratio variable during cpu operation wait for clock oscillation stabilization crystal/ceramic oscillation selected by option byte reset by power-on clear remark pcc: processor clock control register ppcc: preprocessor clock control register (3) external clock input circuit if external clock input is selected by t he option byte, the following is possible. ? high-speed operation the accuracy of processing is improved as compared with high-speed ring-osc oscillation (8 mhz (typ.)) because an oscillation frequency of 500 khz to 10 mhz can be selected and an external clock with a small frequency deviation can be supplied. ? improvement of expandability if the external clock input circuit is selected as the osci llator, the x2 pin can be used as an i/o port pin. for details, refer to chapter 4 port functions . figures 5-14 and 5-15 show the timing chart and status tr ansition diagram of default start by external clock input. www..net
chapter 5 clock generators preliminary user?s manual u16898ej1v0ud 76 figure 5-14. timing of default start by external clock input v dd (a) (b) external clock input pcc = 02h, ppcc = 02h h reset system clock internal reset cpu clock option byte is read. system clock is selected. (operation stops: 8/f rl + 96/f rh ) remark f rl : low-speed ring-osc clock oscillation frequency f rh : high-speed ring-osc clock oscillation frequency (a) the internal reset signal is generated by the power- on clear function on power application, the option byte is referenced after reset, and the system clock is selected. (b) the option byte is referenced and the system clock is selected. then the external clock operates as the system clock. figure 5-15. status transition of de fault start by external clock input halt stop halt instruction stop instruction v dd > 2.1 v 0.1 v start with pcc = 02h, ppcc = 02h interrupt reset signal interrupt power application reset by power-on clear external clock input selected by option byte clock division ratio variable during cpu operation remark pcc: processor clock control register ppcc: preprocessor clock control register www..net
chapter 5 clock generators preliminary user?s manual u16898ej1v0ud 77 5.6 operation of clock generator s upplying clock to peripheral hardware the following two types of clocks are supplied to the peripheral hardware. ? clock to peripheral hardware (f xp ) ? low-speed ring-osc clock (f rl ) (1) clock to peripheral hardware the clock to the peripheral hardware is supplied by dividing the system clock (f x ). the division ratio is selected by the pre-processor clock control register (ppcc). three types of frequencies are selectable: ?f x ?, ?f x /2?, and ?f x /2 2 ?. table 5-3 lists the clocks supplied to the peripheral hardware. table 5-3. clocks to peripheral hardware ppcc1 ppcc0 selection of clock to peripheral hardware (f xp ) 0 0 f x 0 1 f x /2 1 0 f x /2 2 1 1 setting prohibited (2) low-speed ring-osc clock the low-speed ring-osc oscillator of the clock oscillator for interval time generation is always started after release of reset, and oscillates at 240 khz (typ.). it can be specified by the option byte whether the low- speed ring-osc oscillator can or cannot be stopped by software. if it is specified that the low-speed ring-os c oscillator can be stopped by software, oscillation can be started or stopped by usi ng the low-speed ring-osc mode register (lsrcm). if it is specif ied that it cannot be stopped by software, the clock source of wdt is fixed to the low-speed ring-osc clock (frl). the low-speed ring-osc oscillator is inde pendent of the cpu clock. if it is used as the source clock of wdt, therefore, a hang-up can be det ected even if the cpu cloc k is stopped. if the low-speed ring-osc oscillator is used as a count clock source of 8-bit timer h1, 8-bi t timer h1 can operate even in the standby status. table 5-4 shows the operation status of the low-speed ring-osc oscillator when it is selected as the source clock of wdt and the count clock of 8-bit timer h1. fi gure 5-16 shows the status tr ansition of the low-speed ring-osc oscillator. table 5-4. operation status of low-speed ring-osc oscillator option byte setting cpu status wdt status tmh1 status lsrstop = 1 stopped stopped lsrstop = 0 operation mode operates operates lsrstop = 1 stopped stopped can be stopped by software lsrstop = 0 standby stopped operates operation mode cannot be stopped standby operates www..net
chapter 5 clock generators preliminary user?s manual u16898ej1v0ud 78 figure 5-16. status transition of low-speed ring-osc oscillator lsrstop = 0 cannot be stopped can be stopped clock source of wdt is selected by software note clock source of wdt is fixed to f rl low-speed ring-osc oscillator can be stopped low-speed ring-osc oscillator cannot be stopped low-speed ring-osc oscillator stops lsrstop = 1 v dd > 2.1 v 0.1 v reset signal power application reset by power-on clear select by option byte if low-speed ring-osc can be stopped or not note the clock source of the watchdog timer (wdt) is selected from f xp or f rl , or it may be stopped. for details, refer to chapter 9 watchdog timer . www..net
preliminary user?s manual u16898ej1v0ud 79 chapter 6 16-bit timer/event counter 00 6.1 functions of 16-bit timer/event counter 00 16-bit timer/event counter 00 has the following functions. (1) interval timer 16-bit timer/event counter 00 generates interr upt requests at the preset time interval. ? number of counts: 2 to 65536 (2) external event counter 16-bit timer/event counter 00 can measure the number of pulses with a high-/low-level width of a signal input externally. ? valid level pulse width: 16/f xp or more (3) pulse width measurement 16-bit timer/event counter 00 can measure the pulse width of an externally input signal. ? valid level pulse width: 2/f xp or more (4) square-wave output 16-bit timer/event counter 00 can output a square wave with any selected frequency. ? cycle: (2 2 to 65536 2) count clock cycle (5) ppg output 16-bit timer/event counter 00 can output a squar e wave that have arbitrary cycle and pulse width. ? 2 < pulse width < cycle (ffff + 1) h (6) one-shot pulse output 16-bit timer/event counter 00 can out put a one-shot pulse for which output pulse width can be set to any desired value. www..net
chapter 6 16-bit timer/event counter 00 preliminary user?s manual u16898ej1v0ud 80 6.2 configuration of 16-bi t timer/event counter 00 16-bit timer/event counter 00 cons ists of the following hardware. table 6-1. configuration of 16-bit timer/event counter 00 item configuration timer counter 16-bit timer counter 00 (tm00) register 16-bit timer capture/compare registers 000, 010 (cr000, cr010) timer input ti000, ti010 timer output to00, output controller control registers 16-bit timer mode control register 00 (tmc00) capture/compare control register 00 (crc00) 16-bit timer output control register 00 (toc00) prescaler mode register 00 (prm00) port mode register 3 (pm3) port register 3 (p3) figures 6-1 shows a block di agram of these counters. figure 6-1. block diagram of 16-bit timer/event counter 00 internal bus capture/compare control register 00 (crc00) ti010/to00/ intp2/p31 f xp f xp /2 2 f xp /2 8 f x ti000/intp0/p30 prescaler mode register 00 (prm00) 2 prm001 prm000 crc002 16-bit timer capture/compare register 010 (cr010) match match 16-bit timer counter 00 (tm00) clear noise elimi- nator crc002 crc001 crc000 inttm000 to00/ti010/ intp2/p31 inttm010 16-bit timer output control register 00 (toc00) 16-bit timer mode control register 00 (tmc00) internal bus tmc003 tmc002 tmc001 ovf00 toc004 lvs00 lvr00 toc001 toe00 selector 16-bit timer capture/compare register 000 (cr000) selector selector selector noise elimi- nator noise elimi- nator output controller ospe00 ospt00 output latch (p31) pm31 www..net
chapter 6 16-bit timer/event counter 00 preliminary user?s manual u16898ej1v0ud 81 (1) 16-bit timer counter 00 (tm00) tm00 is a 16-bit read-only regist er that counts count pulses. the counter is incremented in synchroni zation with the rising edge of the count clock. if the count value is read during operation, input of t he count clock is temporarily stopped, and t he count value at that point is read. figure 6-2. format of 16-bit timer counter 00 (tm00) tm00 symbol ff13h ff12h address: ff12h, ff13h after reset: 0000h r the count value is reset to 0000h in the following cases. <1> at reset input <2> if tmc003 and tmc002 are cleared <3> if the valid edge of ti000 is input in the clear & start mode entered by inputting the valid edge of ti000 <4> if tm00 and cr000 match in the clear & star t mode entered on a match between tm00 and cr000 <5> if ospt00 is set in the one-shot pulse output mode (2) 16-bit timer capture/comp are register 000 (cr000) cr000 is a 16-bit register which has the functions of both a capture register and a compare register. whether it is used as a capture register or as a compare regist er is set by bit 0 (crc000) of capture/compare control register 00 (crc00). cr000 is set by 16-bit memory manipulation instruction. a reset clears cr000 to 0000h. figure 6-3. format of 16-bit timer ca pture/compare register 000 (cr000) cr000 symbol ff15h ff14h address: ff14h, ff15h after reset: 0000h r/w ? when cr000 is used as a compare register the value set in cr000 is constantly compared with the 16-bit timer/counter 00 (tm 00) count value, and an interrupt request (inttm000) is generat ed if they match. it can also be us ed as the register that holds the interval time then tm00 is set to interval timer operation. ? when cr000 is used as a capture register it is possible to select the valid edge of the ti000 pi n or the ti010 pin as the capture trigger. setting of the ti000 or ti010 valid edge is performed by means of prescaler mode register 00 (prm00) (refer to table 6- 2 ). www..net
chapter 6 16-bit timer/event counter 00 preliminary user?s manual u16898ej1v0ud 82 table 6-2. cr000 capture trigger and valid edges of ti000 and ti010 pins (1) ti000 pin valid edge selected as captu re trigger (crc001 = 1, crc000 = 1) cr000 capture trigger ti000 pin valid edge es010 es000 falling edge rising edge 0 1 rising edge falling edge 0 0 no capture operation both rising and falling edges 1 1 (2) ti010 pin valid edge selected as captu re trigger (crc001 = 0, crc000 = 1) cr000 capture trigger ti010 pin valid edge es110 es100 falling edge falling edge 0 0 rising edge rising edge 0 1 both rising and falling edges both rising and falling edges 1 1 remarks 1. setting es010, es000 = 1, 0 and es110, es100 = 1, 0 is prohibited. 2. es010, es000: bits 5 and 4 of prescaler mode register 00 (prm00) es110, es100: bits 7 and 6 of prescaler mode register 00 (prm00) crc001, crc000: bits 1 and 0 of captur e/compare control register 00 (crc00) cautions 1. set cr000 to a value other than 00 00h in the clear & start mode entered on a match between tm00 and cr000. how ever, in the free-running mode and in the clear & start mode using the valid edge of ti000, if cr0 00 is set to 0000h, an interrupt request (inttm000) is generated when cr000 changes from 0000h to 0001h following overflow (ffffh). 2. if the new value of cr000 is less than th e value of 16-bit timer counter 0 (tm00), tm00 continues counting, overflows, and then starts counting from 0 again. if the new value of cr000 is less than the old value , therefore, the timer must be reset to be restarted after the value of cr000 is changed. 3. when p31 is used as the i nput pin for the valid edge of ti 010, it cannot be used as a timer output (to00). moreover, when p31 is used as to00, it cannot be used as the input pin for the valid edge of ti010. 4. if the register read period and the input of the capture trigger conflict when cr000 is used as a capture register, the read data is undefined (the capture data itself is a normal value). also, if the count stop input and th e input of the capture trigger conflict, the capture trigger is undefined. 5. changing the cr000 setting may cause a malf unction. to change the setting, refer to 6.5 cautions related to 16-bit timer/event c ounter 00 (11) changing compare register during timer operation. www..net
chapter 6 16-bit timer/event counter 00 preliminary user?s manual u16898ej1v0ud 83 (3) 16-bit capture/compare register 010 (cr010) cr010 is a 16-bit register which has the functions of both a capture register and a compare register. whether it is used as a capture register or a compare regist er is set by bit 2 (crc002) of capture/compare control register 00 (crc00). cr010 is set by 16-bit memory manipulation instruction. reset input clears cr010 to 0000h. figure 6-4. format of 16-bit timer ca pture/compare register 010 (cr010) cr010 symbol ff17h ff16h address: ff16h, ff17h after reset: 0000h r/w ? when cr010 is used as a compare register the value set in cr010 is constantly compared with the 16-bit timer count er 00 (tm00) count value, and an interrupt request (inttm010) is generated if they match. ? when cr010 is used as a capture register it is possible to select the valid edge of the ti000 pin as the capture trigger. the ti000 valid edge is set by means of prescaler mode register 00 (prm00) (refer to table 6-3 ). table 6-3. cr010 capture trigger and valid edge of ti000 pin (crc002 = 1) cr010 capture trigger ti000 pin valid edge es010 es000 falling edge falling edge 0 0 rising edge rising edge 0 1 both rising and falling edges both rising and falling edges 1 1 remarks 1. setting es010, es000 = 1, 0 is prohibited. 2. es010, es000: bits 5 and 4 of prescaler mode register 00 (prm00) crc002: bit 2 of capture/com pare control register 00 (crc00) cautions 1. set cr010 to other than 0000h in the clear & start mode entered on a match between tm00 and cr000. however, in the free-running mode and in the clear & start mode using the valid edge of the ti000 pin, if cr010 is set to 0000h, an interru pt request (inttm010) is generated when cr010 changes from 000 0h to 0001h following overflow (ffffh). 2. if the register read period and the input of the capture trigger conflict when cr010 is used as a capture register, the read data is undefined (the capture data itself is a normal value). also, if the count stop input and th e input of the capture trigger conflict, the capture data is undefined. 3 changing the cr010 setting during tm00 opera tion may cause a malfunction. to change the setting, refer to 6.5 cauti ons related to 16-bit timer/event counter 00 (11) changing compare register during timer operation. www..net
chapter 6 16-bit timer/event counter 00 preliminary user?s manual u16898ej1v0ud 84 6.3 registers to control 16- bit timer/event counter 00 the following six types of registers are used to control 16-bit timer/event counter 00. ? 16-bit timer mode control register 00 (tmc00) ? capture/compare control register 00 (crc00) ? 16-bit timer output control register 00 (toc00) ? prescaler mode register 00 (prm00) ? port mode register 3 (pm3) ? port register 3 (p3) (1) 16-bit timer mode control register 00 (tmc00) this register sets the 16-bit timer operating mode, the 16-bit timer count er 00 (tm00) clear mode, and output timing, and detects an overflow. tmc00 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets the value of tmc00 to 00h. caution 16-bit timer counter 00 (tm00) starts operation at the moment tmc002 and tmc003 (operation stop mode) are set to a value other than 0, 0, respectively. set tmc002 and tmc003 to 0, 0 to stop the operation. www..net
chapter 6 16-bit timer/event counter 00 preliminary user?s manual u16898ej1v0ud 85 figure 6-5. format of 16-bit timer mode control register 00 (tmc00) 7 0 6 0 5 0 4 0 3 tmc003 2 tmc002 1 tmc001 <0> ovf00 symbol tmc00 address: ff60h after reset: 00h r/w ovf00 overflow detection of 16-bit timer counter 00 (tm00) 0 overflow not detected 1 overflow detected cautions 1. to write different data to tmc00, stop the ti mer operation before writing. 2. the timer operation must be stopped before writing to bits other than the ovf00 flag. 3. set the valid edge of the ti000/intp0/ p30 pin with prescaler mode register 00 (prm00). 4. if the clear & start mode entered on a matc h between tm00 and cr000, clear & start mode at the valid edge of the ti000 pin, or free-running mode is selected , when the set value of cr000 is ffffh and the tm00 value ch anges from ffffh to 0000h, the ovf00 flag is set to 1. remark tm00: 16-bit timer counter 00 cr000: 16-bit timer capture/compare register 000 cr010: 16-bit timer capture/compare register 010 tmc003 tmc002 tmc001 operating mode and clear mode selection to00 inversion timing selection interrupt request generation 0 0 0 0 0 1 operation stop (tm00 cleared to 0) no change not generated 0 1 0 free-running mode match between tm00 and cr000 or match between tm00 and cr010 0 1 1 match between tm00 and cr000, match between tm00 and cr010 or ti000 valid edge 1 0 0 1 0 1 clear & start occurs on valid edge of ti000 pin ? 1 1 0 clear & start occurs on match between tm00 and cr000 match between tm00 and cr000 or match between tm00 and cr010 1 1 1 match between tm00 and cr000, match between tm00 and cr010 or ti000 valid edge generated on match between tm00 and cr000, or match between tm00 and cr010 www..net
chapter 6 16-bit timer/event counter 00 preliminary user?s manual u16898ej1v0ud 86 (2) capture/compare control register 00 (crc00) this register controls the op eration of the 16-bit capture/co mpare registers (cr000, cr010). crc00 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets the value of crc00 to 00h. figure 6-6. format of capture/co mpare control register 00 (crc00) address: ff62h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 crc00 0 0 0 0 0 crc002 crc001 crc000 crc002 cr010 operating mode selection 0 operate as compare register 1 operate as capture register crc001 cr000 capture trigger selection 0 capture on valid edge of ti010 pin 1 capture on valid edge of ti000 pin by reverse phase crc000 cr000 operating mode selection 0 operate as compare register 1 operate as capture register cautions 1. the timer operation mu st be stopped before setting crc00. 2. when the clear & start mode entered on a match between tm00 and cr000 is selected by 16-bit timer mode control register 00 (t mc00), cr000 should not be specified as a capture register. 3. if both the rising and fal ling edges have been selected as th e valid edges of the ti000 pin, capture is not performed. 4. to ensure the reliability of the capture operation, the capture trigger requires a pulse longer than two cycles of the count clock selected by prescaler mode register 00 (prm00) (refer to figure 6-17). www..net
chapter 6 16-bit timer/event counter 00 preliminary user?s manual u16898ej1v0ud 87 (3) 16-bit timer output control register 00 (toc00) this register controls the operation of the 16-bit timer/ event counter output controller. it sets timer output f/f set/reset, output inversion enable/disable, 16-bit timer/ event counter 00 timer output enable/disable, one-shot pulse output operation enable/disable, and out put trigger of one-shot pulse by software. toc00 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets the value of toc00 to 00h. figure 6-7. format of 16-bit timer ou tput control register 00 (toc00) address: ff63h after reset: 00h r/w symbol 7 <6> <5> 4 <3> <2> 1 <0> toc00 0 ospt00 ospe00 toc004 lvs00 lvr00 toc001 toe00 ospt00 one-shot pulse output trigger control via software 0 no one-shot pulse trigger 1 one-shot pulse trigger ospe00 one-shot pulse output operation control 0 successive pulse output mode 1 one-shot pulse output mode note toc004 timer output f/f control using match of cr010 and tm00 0 disables inversion operation 1 enables inversion operation lvs00 lvr00 timer output f/f status setting 0 0 no change 0 1 timer output f/f reset (0) 1 0 timer output f/f set (1) 1 1 setting prohibited toc001 timer output f/f control using match of cr000 and tm00 0 disables inversion operation 1 enables inversion operation toe00 timer output control 0 disables output (output fixed to level 0) 1 enables output note the one-shot pulse output mode op erates correctly only in the free-running mode and the mode in which clear & start occurs at the ti000 pin valid edge. in the mode in which clear & start occurs on a match between tm00 and cr000, one-shot pul se output is not possible because an overflow does not occur. cautions 1. timer operation must be st opped before setting other than ospt00. 2. if lvs00 and lvr00 are read, 0 is read. 3. ospt00 is automatically cleared after data is set, so 0 is read. 4. do not set ospt00 to 1 other than in one-shot pulse output mode. 5. a write interval of two cycles or more of th e count clock selected by prescaler mode register 00 (prm00) is required to write to ospt00 successively. www..net
chapter 6 16-bit timer/event counter 00 preliminary user?s manual u16898ej1v0ud 88 (4) prescaler mode register 00 (prm00) this register is used to set the 16-bit timer counter 00 (tm00) count clock and the ti000, ti010 pin input valid edges. prm00 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets the value of prm00 to 00h. figure 6-8. format of prescaler mode register 00 (prm00) address: ff61h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 prm00 es110 es100 es010 es000 0 0 prm001 prm000 es110 es100 ti010 pin valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges es010 es000 ti000 pin valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges prm001 prm000 count clock selection 0 0 f xp (10 mhz) 0 1 f xp /2 2 (2.5 mhz) 1 0 f xp /2 8 (39.06 khz) 1 1 ti000 pin valid edge note note the external clock requires a pulse longer than two cycles of the internal count clock (f xp ). cautions 1. always set data to prm 00 after stopping the timer operation. 2. if the valid edge of the ti000 pin is to be set as the count clock, do not set the clear/start mode and the capture trigger at th e valid edge of the ti000 pin. 3. if the ti000 or ti010 pin is high level imme diately after system reset, the rising edge is immediately detected after the rising edge or both the rising and falling edges are set as the valid edge(s) of the ti000 pin or ti010 pin to enable the operation of 16-bit timer counter 00 (tm00). be carefu l when pulling up the ti000 pin or the ti010 pin. however, when re-enabling operation afte r the operation has been stopped once, the rising edge is not detected. 4. when using p31 as the input pin of the ti 010 pin valid edge, it cannot be used as a timer output (to00). when using p31 as the to00 pin, it cannot be used as the input pin of the ti010 pin valid edge. remarks 1. f xp : oscillation frequency of clock supplied to peripheral hardware 2. ( ): f xp = 10 mhz www..net
chapter 6 16-bit timer/event counter 00 preliminary user?s manual u16898ej1v0ud 89 (5) port mode register 3 (pm3) this register sets port 3 input/output in 1-bit units. when using the p31/to00/ti010/intp2 pin for timer out put, set pm31 and the output latch of p31 to 0. when using the p30/ti000/intp0 and p31/to00/ti010/intp2 pins as a timer input, set pm30 and pm31 to 1. at this time, the output latches of p30 and p31 can be either 0 or 1. pm3 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets the value of pm3 to ffh. figure 6-9. format of port mode register 3 (pm3) 7 1 6 1 5 1 4 1 3 1 2 1 1 pm31 0 pm30 symbol pm3 address: ff23h after reset: ffh r/w pm3n 0 1 p3n pin i/o mode selection (n = 0 or 1) output mode (output buffer on) input mode (output buffer off) www..net
chapter 6 16-bit timer/event counter 00 preliminary user?s manual u16898ej1v0ud 90 6.4 operation of 16-bit timer/event counter 00 6.4.1 interval timer operation setting 16-bit timer mode control register 00 (tmc00) and capture/compare control register 00 (crc00) as shown in figure 6-10 allows operation as an interval timer. setting the basic operation setting procedure is as follows. <1> set the crc00 register (see figure 6-10 for the set value). <2> set any value to the cr000 register. <3> set the count clock by using the prm00 register. <4> set the tmc00 register to start the operation (see figure 6-10 for the set value). caution changing the cr000 setti ng during tm00 operation may cause a malfunction. to change the setting, refer to 6.5 cautions related to 16-bi t timer/event counter 00 (11) changing compare register during timer operation. remark for how to enable the inttm000 interrupt, see chapter 12 interrupt functions . interrupt requests are generated repeatedly using the count value set in 16-bit timer capture/compare register 000 (cr000) beforehand as the interval. when the count value of 16-bit timer counter 00 (tm00) matches the value set to cr000, counting continues with the tm00 value cleared to 0 and the interrupt request signal (inttm000) is generated. the count clock of the 16-bit timer/ev ent counter can be selected using bits 0 and 1 (prm000, prm001) of prescaler mode register 00 (prm00). www..net
chapter 6 16-bit timer/event counter 00 preliminary user?s manual u16898ej1v0ud 91 figure 6-10. control register setti ngs for interval timer operation (a) 16-bit timer mode control register 00 (tmc00) 7 0 6 0 5 0 4 0 tmc003 1 tmc002 1 tmc001 0/1 ovf00 0 tmc00 clears and starts on match between tm00 and cr000. (b) capture/compare cont rol register 00 (crc00) 7 0 6 0 5 0 4 0 3 0 crc002 0/1 crc001 0/1 crc000 0 crc00 cr000 used as compare register (c) prescaler mode register 00 (prm00) es110 0/1 es100 0/1 es010 0/1 es000 0/1 3 0 2 0 prm001 0/1 prm000 0/1 prm00 selects count clock. setting invalid (setting ?10? is prohibited.) setting invalid (setting ?10? is prohibited.) remark 0/1: setting 0 or 1 allows another function to be us ed simultaneously with the interval timer. see the description of the respective control registers for details. www..net
chapter 6 16-bit timer/event counter 00 preliminary user?s manual u16898ej1v0ud 92 figure 6-11. interval ti mer configuration diagram 16-bit timer capture/compare register 000 (cr000) 16-bit timer counter 00 (tm00) ovf00 clear circuit inttm000 f xp f xp /2 2 f xp /2 8 ti000/intp0/p30 selector noise eliminator f xp note note ovf00 is set to 1 only when 16-bit timer capt ure/compare register 000 is set to ffffh. figure 6-12. timing of interval timer operation count clock t tm00 count value cr000 inttm000 0000h 0001h n 0000h 0001h n 0000h 0001h n n n n n timer operation enabled clear clear interrupt acknowledged interrupt acknowledged remark interval time = (n + 1) t n = 0001h to ffffh when the compare register is changed during timer count o peration, if the value after 16-bit timer capture/compare register 000 (cr000) is changed is smaller than that of 16-bit timer counter 00 (tm00), tm00 continues counting, overflows and then restarts counting from 0. thus, if the value (m) after the cr000 change is smaller than that (n) before the change, it is necessary to restart the timer after changing cr000. figure 6-13. timing after change of comp are register during timer count operation cr000 nm count clock tm00 count value x ? 1 x ffffh 0000h 0001h 0002h remark n > x > m www..net
chapter 6 16-bit timer/event counter 00 preliminary user?s manual u16898ej1v0ud 93 6.4.2 external event counter operation setting the basic operation setting procedure is as follows. <1> set the crc00 register (see figure 6-14 for the set value). <2> set the count clock by using the prm00 register. <3> set any value to the cr000 register (0000h cannot be set). <4> set the tmc00 register to start the operation (see figure 6-14 for the set value). remarks 1. for the setting of the ti000 pin, see 6.3 (5) port mode register 3 (pm3) . 2. for how to enable the inttm000 interrupt, see chapter 12 interrupt functions . the external event counter c ounts the number of external clock pulses to be input to the ti000 pin with using 16-bit timer counter 00 (tm00). tm00 is incremented each time the valid edge specified by prescaler mode register 00 (prm00) is input. when the tm00 count value matches the 16-bit timer capt ure/compare register 000 (cr000) value, tm00 is cleared to 0 and the interrupt requ est signal (inttm000) is generated. input a value other than 0000h to cr000. (a c ount operation with a pulse cannot be carried out.) the rising edge, the falling edge, or both edges can be selected using bits 4 and 5 (es000 and es010) of prescaler mode register 00 (prm00). because an operation is carried out only when the valid ed ge of the ti000 pin is detec ted twice after sampling with the internal clock (f xp ), noise with a short pulse width can be removed. www..net
chapter 6 16-bit timer/event counter 00 preliminary user?s manual u16898ej1v0ud 94 figure 6-14. control register setti ngs in external event counter mode (with rising edge specified) (a) 16-bit timer mode control register 00 (tmc00) 7 0 6 0 5 0 4 0 tmc003 1 tmc002 1 tmc001 0/1 ovf00 0 tmc00 clears and starts on match between tm00 and cr000. (b) capture/compare cont rol register 00 (crc00) 7 0 6 0 5 0 4 0 3 0 crc002 0/1 crc001 0/1 crc000 0 crc00 cr000 used as compare register (c) prescaler mode register 00 (prm00) es110 0/1 es100 0/1 es010 0 es000 1 3 0 2 0 prm001 1 prm000 1 prm00 selects external clock. specifies rising edge for pulse width detection. setting invalid (setting ?10? is prohibited.) remark 0/1: setting 0 or 1 allows another function to be used simultaneously with the external event counter. see the description of the respecti ve control registers for details. www..net
chapter 6 16-bit timer/event counter 00 preliminary user?s manual u16898ej1v0ud 95 figure 6-15. external event counter configuration diagram 16-bit timer capture/compare register 000 (cr000) 16-bit timer counter 00 (tm00) internal bus match clear ovf00 note inttm000 noise eliminator f xp valid edge of ti000 note ovf00 is 1 only when 16-bit timer capt ure/compare register 000 is set to ffffh. figure 6-16. external event counter oper ation timing (with rising edge specified) ti000 pin input tm00 count value cr000 inttm000 0000h 0001h 0002h 0003h 0004h 0005h n?1 n 0000h 0001h 0002h 0003h n caution when reading the ext ernal event counter count value, tm00 should be read. www..net
chapter 6 16-bit timer/event counter 00 preliminary user?s manual u16898ej1v0ud 96 6.4.3 pulse width measurement operations it is possible to measure the pulse width of the signals input to the ti000 pin and ti010 pin using 16-bit timer counter 00 (tm00). there are two measurement methods: measuring with tm00 used in free-running mode, and measuring by restarting the timer in synchronization with th e edge of the signal in put to the ti000 pin. when an interrupt occurs, read the valid value of the capt ure register, check the overflow flag, and then calculate the necessary pulse width. clear the overflow flag after checking it. the capture operation is not performed unt il the signal pulse width is sampl ed in the count clock cycle selected by prescaler mode register 00 (prm00) and the valid level of the ti000 or ti010 pin is dete cted twice, thus eliminating noise with a short pulse width. figure 6-17. cr010 capture operat ion with rising edge specified count clock tm00 ti000 rising edge detection cr010 inttm010 n ? 3n ? 2n ? 1 n n + 1 n setting the basic operation setting procedure is as follows. <1> set the crc00 register (see figures 6-18 , 6-21 , 6-23 , and 6-25 for the set value). <2> set the count clock by using the prm00 register. <3> set the tmc00 register to start the operation (see figures 6-18 , 6-21 , 6-23 , and 6-25 for the set value). caution to use two capture regist ers, set the ti000 and ti010 pins. remarks 1. for the setting of the ti000 (or ti010) pin, see 6.3 (5) port mode register 3 (pm3) . 2. for how to enable the inttm000 (or inttm010) interrupt, see chapter 12 interrupt functions . www..net
chapter 6 16-bit timer/event counter 00 preliminary user?s manual u16898ej1v0ud 97 (1) pulse width measurement with free-runni ng counter and one capture register when 16-bit timer counter 00 (tm00) is operated in fr ee-running mode, and the edge specified by prescaler mode register 00 (prm00) is input to the ti000 pin, the value of tm00 is taken into 16-bit timer capture/compare register 010 (cr010) and an exte rnal interrupt request signal (inttm010) is set. specify both the rising and falling edges by usi ng bits 4 and 5 (es000 and es010) of prm00. sampling is performed using the count clock selected by prm00, and a capture operation is only performed when a valid level of the ti000 pin is detected twic e, thus eliminating noise with a short pulse width. figure 6-18. control register settings for pul se width measurement with free-running counter and one capture register (when ti000 and cr010 are used) (a) 16-bit timer mode control register 00 (tmc00) 7 0 6 0 5 0 4 0 tmc003 0 tmc002 1 tmc001 0/1 ovf00 0 tmc00 free-running mode (b) capture/compare cont rol register 00 (crc00) 7 0 6 0 5 0 4 0 3 0 crc002 1 crc001 0/1 crc000 0 crc00 cr000 used as compare register cr010 used as capture register (c) prescaler mode register 00 (prm00) es101 0/1 es100 0/1 es010 1 es000 1 3 0 2 0 prm001 0/1 prm000 0/1 prm00 selects count clock (setting ?11? is prohibited). specifies both edges for pulse width detection. setting invalid (setting ?10? is prohibited.) remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. see the description of the respecti ve control registers for details. www..net
chapter 6 16-bit timer/event counter 00 preliminary user?s manual u16898ej1v0ud 98 figure 6-19. configuration di agram for pulse width measure ment by free-running counter f xp f xp /2 2 f xp /2 6 ti000/intp0/p30 16-bit timer/counter 00 (tm00) ovf00 16-bit timer capture/compare register 010 (cr010) internal bus inttm010 selector figure 6-20. timing of pulse width measure ment operation by free-running counter and one capture register (with both edges specified) t 0000h 0000h ffffh 0001h d0 d0 (d1 ? d0) t (d3 ? d2) t (10000h ? d1 + d2) t d1 d2 d3 d2 d3 d0 + 1 d1 d1 + 1 note count clock tm00 count value ti000 pin input cr010 capture value inttm010 ovf00 note ovf00 must be cleared by software. www..net
chapter 6 16-bit timer/event counter 00 preliminary user?s manual u16898ej1v0ud 99 (2) measurement of two pulse widths with free-running counter when 16-bit timer counter 00 (tm00) is operated in fr ee-running mode, it is possible to simultaneously measure the pulse widths of the two signal s input to the ti000 pin and the ti010 pin. when the edge specified by bits 4 and 5 (es000 and es0 10) of prescaler mode register 00 (prm00) is input to the ti000 pin, the value of tm00 is taken into 16-bit timer capture/compare register 010 (cr010) and an interrupt request signal (inttm010) is set. also, when the edge specified by bits 6 and 7 (es100 and es110) of prm00 is input to the ti010 pin, the value of tm00 is taken into 16-bit timer capture/co mpare register 000 (cr000) and an interrupt request signal (inttm000) is set. specify both the rising and falling edges as the edge s of the ti000 and ti010 pins, by using bits 4 and 5 (es000 and es010) and bits 6 and 7 (es100 and es110) of prm00. sampling is performed using the count clock cycle sele cted by prescaler mode register 00 (prm00), and a capture operation is only performed when a valid level of the ti000 or ti010 pin is detected twice, thus eliminating noise with a short pulse width. figure 6-21. control register settings for measure ment of two pulse widths with free-running counter (a) 16-bit timer mode control register 00 (tmc00) 7 0 6 0 5 0 4 0 tmc003 0 tmc002 1 tmc001 0/1 ovf00 0 tmc00 free-running mode (b) capture/compare cont rol register 00 (crc00) 7 0 6 0 5 0 4 0 3 0 crc002 1 crc001 0 crc000 1 crc00 cr000 used as capture register captures valid edge of ti010 pin to cr000. cr010 used as capture register (c) prescaler mode register 00 (prm00) es110 1 es100 1 es010 1 es000 1 3 0 2 0 prm001 0/1 prm000 0/1 prm00 selects count clock (setting ?11? is prohibited). specifies both edges for pulse width detection. specifies both edges for pulse width detection. remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. see the description of the respecti ve control registers for details. www..net
chapter 6 16-bit timer/event counter 00 preliminary user?s manual u16898ej1v0ud 100 figure 6-22. timing of pulse width measureme nt operation with free-running counter (with both edges specified) t 0000h 0000h ffffh 0001h d0 d0 (d1 ? d0) t (d3 ? d2) t (10000h ? d1 + d2) t (10000h ? d1 + (d2 + 1)) t d1 d2 + 1 d1 d2 d2 d3 d0 + 1 d1 d1 + 1 d2 + 1 d2 + 2 note ti010 pin input cr000 capture value inttm010 inttm000 ovf00 count clock tm00 count value ti000 pin input cr010 capture value note ovf00 must be cleared by software. www..net
chapter 6 16-bit timer/event counter 00 preliminary user?s manual u16898ej1v0ud 101 (3) pulse width measurement with free-runni ng counter and two capture registers when 16-bit timer counter 00 (tm00) is operated in free-running mode, it is possible to measure the pulse width of the signal input to the ti000 pin. when the rising or falling edge specified by bits 4 an d 5 (es000 and es010) of prescaler mode register 00 (prm00) is input to the ti000 pin, the value of tm00 is taken into 16-bit timer capture/compare register 010 (cr010) and an interrupt request signal (inttm010) is set. also, when the inverse edge to that of the capture operation is input into cr010, the value of tm00 is taken into 16-bit timer capture/compare register 000 (cr000). sampling is performed using the count clock cycle sele cted by prescaler mode register 00 (prm00), and a capture operation is only performed when a valid level of the ti000 pin is detected twice, thus eliminating noise with a short pulse width. figure 6-23. control register settings for pulse width measurement with fr ee-running counter and two capture registers (with rising edge specified) (a) 16-bit timer mode control register 00 (tmc00) 7 0 6 0 5 0 4 0 tmc003 0 tmc002 1 tmc001 0/1 ovf00 0 tmc00 free-running mode (b) capture/compare cont rol register 00 (crc00) 7 0 6 0 5 0 4 0 3 0 crc002 1 crc001 1 crc000 1 crc00 cr000 used as capture register captures to cr000 at inverse edge to valid edge of ti000. cr010 used as capture register (c) prescaler mode register 00 (prm00) es110 0/1 es100 0/1 es010 0 es000 1 3 0 2 0 prm001 0/1 prm000 0/1 prm00 selects count clock (setting ?11? is prohibited). specifies rising edge for pulse width detection. setting invalid (setting ?10? is prohibited.) remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. see the description of the respecti ve control registers for details. www..net
chapter 6 16-bit timer/event counter 00 preliminary user?s manual u16898ej1v0ud 102 figure 6-24. timing of pulse width measure ment operation by free-running counter and two capture registers (with rising edge specified) t 0000h 0000h ffffh 0001h d0 d0 d2 d1 d3 d2 d3 d1 d0 + 1 d2 + 1 d1 + 1 inttm010 ovf00 cr000 capture value count clock tm00 count value ti000 pin input cr010 capture value (d1 ? d0) t (d3 ? d2) t (10000h ? d1 + d2) t note note ovf00 must be cleared by software. (4) pulse width measurement by means of restart when input of a valid edge to the ti 000 pin is detected, the count value of 16-bit timer/counter 00 (tm00) is taken into 16-bit timer capture/compare register 010 ( cr010), and then the pulse width of the signal input to the ti000 pin is measured by clear ing tm00 and restarting the count. the edge specification can be selected from two types, rising or falling edges, by bits 4 and 5 (es000 and es010) of prescaler mode register 00 (prm00) sampling is performed at the interval selected by pr escaler mode register 00 (prm 00) and a capture operation is only performed when a valid level of the ti000 pin is detected twice, thus eliminating noise with a short pulse width. caution if the valid edge of ti 000 is specified to be both the ri sing and falling edges, 16-bit timer capture/compare register 000 (cr000) cannot perform the capture operation. www..net
chapter 6 16-bit timer/event counter 00 preliminary user?s manual u16898ej1v0ud 103 figure 6-25. control register settings for pu lse width measurement by means of restart (with rising edge specified) (a) 16-bit timer mode control register 00 (tmc00) 7 0 6 0 5 0 4 0 tmc003 1 tmc002 0 tmc001 0/1 ovf00 0 tmc00 clears and starts at valid edge of ti000 pin. (b) capture/compare cont rol register 00 (crc00) 7 0 6 0 5 0 4 0 3 0 crc002 1 crc001 1 crc000 1 crc00 cr000 used as capture register captures to cr000 at inverse edge to valid edge of ti000. cr010 used as capture register (c) prescaler mode register 00 (prm00) es110 0/1 es100 0/1 es010 0 es000 1 3 0 2 0 prm001 0/1 prm000 0/1 prm00 selects count clock (setting ?11? is prohibited). specifies rising edge for pulse width detection. setting invalid (setting ?10? is prohibited.) figure 6-26. timing of pulse width measure ment operation by means of restart (with rising edge specified) t 0000h 0001h 0000h 0001h 0000h 0001h d0 d0 inttm010 d1 t d2 t d2 d1 d2 d1 cr000 capture value count clock tm00 count value ti000 pin input cr010 capture value www..net
chapter 6 16-bit timer/event counter 00 preliminary user?s manual u16898ej1v0ud 104 6.4.4 square-wave output operation setting the basic operation setting procedure is as follows. <1> set the count clock by using the prm00 register. <2> set the crc00 register (see figure 6-27 for the set value). <3> set the toc00 register (see figure 6-27 for the set value). <4> set any value to the cr000 register (0000h cannot be set). <5> set the tmc00 register to start the operation (see figure 6-27 for the set value). caution changing the cr000 setti ng during tm00 operation may cause a malfunction. to change the setting, refer to 6.5 cautions related to 16-bi t timer/event counter 00 (11) changing compare register during timer operation. remarks 1. for the setting of the to00 pin, see 6.3 (5) port mode register 3 (pm3) . 2. for how to enable the inttm000 interrupt, see chapter 12 interrupt functions . a square wave with any selected frequency can be output at intervals determined by the count value preset to 16- bit timer capture/compare register 000 (cr000). the to00 pin output status is reversed at intervals determined by the count value preset to cr000 + 1 by setting bit 0 (toe00) and bit 1 (toc001) of 16-bit timer output control register 00 (toc00) to 1. this enables a square wave with any selected frequency to be output. figure 6-27. control register settings in square-wave output mode (1/2) (a) 16-bit timer mode control register 00 (tmc00) 7 0 6 0 5 0 4 0 tmc003 1 tmc002 1 tmc001 0 ovf00 0 tmc00 clears and starts on match between tm00 and cr000. (b) capture/compare cont rol register 00 (crc00) 7 0 6 0 5 0 4 0 3 0 crc002 0/1 crc001 0/1 crc000 0 crc00 cr000 used as compare register www..net
chapter 6 16-bit timer/event counter 00 preliminary user?s manual u16898ej1v0ud 105 figure 6-27. control register settings in square-wave output mode (2/2) (c) 16-bit timer output control register 00 (toc00) 7 0 ospt00 0 ospe00 0 toc004 0 lvs00 0/1 lvr00 0/1 toc001 1 toe00 1 toc00 enables to00 output. inverts output on match between tm00 and cr000. specifies initial value of to00 output f/f (setting ?11? is prohibited). does not invert output on match between tm00 and cr010. disables one-shot pulse output. (d) prescaler mode register 00 (prm00) es110 0/1 es100 0/1 es010 0/1 es000 0/1 3 0 2 0 prm001 0/1 prm000 0/1 prm00 selects count clock. setting invalid (setting ?10? is prohibited.) setting invalid (setting ?10? is prohibited.) remark 0/1: setting 0 or 1 allows another function to be used simultaneously with square-wave output. see the description of the respective control registers for details. figure 6-28. square-wave output operation timing count clock tm00 count value cr000 inttm000 to00 pin output 0000h 0001h 0002h n ? 1n 0000h 0001h 0002h n ? 1n 0000h n www..net
chapter 6 16-bit timer/event counter 00 preliminary user?s manual u16898ej1v0ud 106 6.4.5 ppg output operations setting 16-bit timer mode control register 00 (tmc00) and capture/compare control register 00 (crc00) as shown in figure 6-29 allows operation as ppg (programmable pulse generator) output. setting the basic operation setting procedure is as follows. <1> set the crc00 register (see figure 6-29 for the set value). <2> set any value to the cr000 register as the cycle. <3> set any value to the cr010 register as the duty factor. <4> set the toc00 register (see figure 6-29 for the set value). <5> set the count clock by using the prm00 register. <6> set the tmc00 register to start the operation (see figure 6-29 for the set value). caution changing the crc0n0 setti ng during tm00 operation may cause a malfunction. to change the setting, refer to 6.5 cautions related to 16-bit timer/event counter 00 (11) changing compare register during timer operation. remarks 1. for the setting of the to00 pin, see 6.3 (5) port mode register 3 (pm3) . 2. for how to enable the inttm000 interrupt, see chapter 12 interrupt functions . 3. n = 0 or 1 in the ppg output oper ation, rectangular wa ves are output from the to00 pin with the pulse wi dth and the cycle that correspond to the count values preset in 16-bit time r capture/compare register 010 (cr010) and in 16-bit timer capture/compare register 000 (cr000), respectively. www..net
chapter 6 16-bit timer/event counter 00 preliminary user?s manual u16898ej1v0ud 107 figure 6-29. control register settings for ppg output operation (a) 16-bit timer mode control register 00 (tmc00) 7 0 6 0 5 0 4 0 tmc003 1 tmc002 1 tmc001 0 ovf00 0 tmc00 clears and starts on match between tm00 and cr000. (b) capture/compare cont rol register 00 (crc00) 7 0 6 0 5 0 4 0 3 0 crc002 0 crc001 crc000 0 crc00 cr000 used as compare register cr010 used as compare register (c) 16-bit timer output control register 00 (toc00) 7 0 ospt00 0 ospe00 0 toc004 1 lvs00 0/1 lvr00 0/1 toc001 1 toe00 1 toc00 enables to00 output. inverts output on match between tm00 and cr000. specifies initial value of to00 output f/f (setting "11" is prohibited). inverts output on match between tm00 and cr010. disables one-shot pulse output. (d) prescaler mode register 00 (prm00) es110 0/1 es100 0/1 es010 0/1 es000 0/1 3 0 2 0 prm001 0/1 prm000 0/1 prm00 selects count clock. setting invalid (setting ?10? is prohibited.) setting invalid (setting ?10? is prohibited.) cautions 1. values in the following ra nge should be set in cr000 and cr010: 0000h cr010 < cr000 ffffh (setting cr000 to 0000h is prohibited.) 2. the cycle of the pulse generated through ppg output (cr000 setting value + 1) has a duty of (cr010 setting value + 1)/(cr000 setting value + 1). remark : don?t care www..net
chapter 6 16-bit timer/event counter 00 preliminary user?s manual u16898ej1v0ud 108 figure 6-30. configuration diagram of ppg output 16-bit timer capture/compare register 000 (cr000) 16-bit timer counter 00 (tm00) clear circuit noise eliminator f xp f xp f xp /2 2 f xp /2 8 ti000/intp0/p30 16-bit timer capture/compare register 010 (cr010) to00/ti010/ intp2/p31 selector output controller figure 6-31. ppg output operation timing t 0000h 0000h 0001h 0001h m ? 1 count clock tm00 count value to00 pulse width: (m + 1) t 1 cycle: (n + 1) t n cr000 capture value cr010 capture value m m n ? 1 n n clear clear remark 0000h m < n ffffh www..net
chapter 6 16-bit timer/event counter 00 preliminary user?s manual u16898ej1v0ud 109 6.4.6 one-shot pulse output operation 16-bit timer/event counter 00 can output a one-shot pulse in synchronization with a software trigger or an external trigger (ti000 pin input). setting the basic operation setting procedure is as follows. <1> set the count clock by using the prm00 register. <2> set the crc00 register (see figures 6-32 and 6-34 for the set value). <3> set the toc00 register (see figures 6-32 and 6-34 for the set value). <4> set any value to the cr000 and cr010 registers (0000h cannot be set). <5> set the tmc00 register to start the operation (see figures 6-32 and 6-34 for the set value). remarks 1. for the setting of the to00 pin, see 6.3 (5) port mode register 3 (pm3) . 2. for how to enable the inttm000 (if necessary, inttm010) interrupt, see chapter 12 interrupt functions . (1) one-shot pulse output with software trigger a one-shot pulse can be output from the to00 pin by setting 16-bit timer mode control register 00 (tmc00), capture/compare control register 00 (crc00), and 16-bit ti mer output control register 00 (toc00) as shown in figure 6-32, and by setting bit 6 (ospt00) of the toc00 register to 1 by software. by setting the ospt00 bit to 1, 16-bit timer/event count er 00 is cleared and start ed, and its output becomes active at the count value (n) set in advance to 16-bit timer capture/compare register 010 (cr010). after that, the output becomes inactive at the count value (m) set in advance to 16-bit timer capture/compare register 000 (cr000) note . even after the one-shot pulse has been output, the tm00 r egister continues its operat ion. to stop the tm00 register, the tmc003 and tmc002 bits of the tmc00 register must be cleared to 00. note the case where n < m is described here. w hen n > m, the output becom es active with the cr000 register and inactive with the cr010 register. do not set n to m. cautions 1. do not set the ospt00 bit while the one-shot pulse is being output. to output the one-shot pulse again, wait until the current one-s hot pulse output is completed. 2. when using the one-shot pulse output of 16-bit timer/event counter 00 with a software trigger, do not change the level of the ti000 pin or its alternate-function port pin. because the external trigger is valid even in this case, the ti mer is cleared and started even at the level of the ti000 pin or its alternate -function port pin, resulting in the output of a pulse at an undesired timing. www..net
chapter 6 16-bit timer/event counter 00 preliminary user?s manual u16898ej1v0ud 110 figure 6-32. control register settings for on e-shot pulse output with software trigger (a) 16-bit timer mode control register 00 (tmc00) 0000 7654 0 tmc003 tmc00 tmc002 tmc001 ovf00 free-running mode 100 (b) capture/compare cont rol register 00 (crc00) 00000 76543 crc00 crc002 crc001 crc000 cr000 as compare register cr010 as compare register 0 0/1 0 (c) 16-bit timer output control register 00 (toc00) 0 7 0 1 1 0/1 toc00 lvr00 lvs00 toc004 ospe00 ospt00 toc001 toe00 enables to00 output. inverts output upon match between tm00 and cr000. specifies initial value of to00 output f/f (setting ?11? is prohibited.) inverts output upon match between tm00 and cr010. sets one-shot pulse output mode. set to 1 for output. 0/1 1 1 (d) prescaler mode register 00 (prm00) 0/1 0/1 0/1 0/1 0 prm00 prm001 prm010 selects count clock. setting invalid (setting ?10? is prohibited.) 0 0/1 0/1 es110 es100 es010 es000 setting invalid (setting ?10? is prohibited.) 32 caution do not set 0000h to the cr000 and cr010 registers. www..net
chapter 6 16-bit timer/event counter 00 preliminary user?s manual u16898ej1v0ud 111 figure 6-33. timing of one-shot pulse output operation with software trigger 0000h n nn n n mm m m nm n + 1 n ? 1m ? 1 0001h m + 1 m + 2 0000h count clock tm00 count cr010 set value cr000 set value ospt00 inttm010 inttm000 to00 pin output set tmc00 to 0ch (tm00 count starts) caution 16-bit timer counter 00 st arts operating as soon as a value other than 00 (operation stop mode) is set to the tmc003 and tmc002 bits. remark n < m (2) one-shot pulse output with external trigger a one-shot pulse can be output from the to00 pin by setting 16-bit timer mode control register 00 (tmc00), capture/compare control register 00 (crc00), and 16-bit ti mer output control register 00 (toc00) as shown in figure 6-34, and by using the valid edge of the ti000 pin as an external trigger. the valid edge of the ti000 pin is specified by bits 4 and 5 (es000, es010) of prescaler mode register 00 (prm00). the rising, falling, or both the rising and falling edges can be specified. when the valid edge of the ti000 pin is detected, the 16-b it timer/event counter is cleared and started, and the output becomes active at the count value set in adv ance to 16-bit timer capture/compare register 010 (cr010). after that, the output becomes inactive at the count value set in advance to 16-bit timer capture/compare register 000 (cr000) note . note the case where n < m is described here. when n > m, the output becomes active with the cr000 register and inactive with the cr010 register. do not set n to m. caution even if the external tr igger is generated again while th e one-shot pulse is output, it is ignored. www..net
chapter 6 16-bit timer/event counter 00 preliminary user?s manual u16898ej1v0ud 112 figure 6-34. control register settings for on e-shot pulse output with external trigger (with rising edge specified) (a) 16-bit timer mode control register 00 (tmc00) 0000 7654 1 tmc003 tmc00 tmc002 tmc001 ovf00 clears and starts at valid edge of ti000 pin. 000 (b) capture/compare cont rol register 00 (crc00) 00000 76543 crc00 crc002 crc001 crc000 cr000 used as compare register cr010 used as compare register 0 0/1 0 (c) 16-bit timer output control register 00 (toc00) 0 7 01 1 0/1 toc00 lvr00 toc001 toe00 ospe00 ospt00 toc004 lvs00 enables to00 output. inverts output upon match between tm00 and cr000. specifies initial value of to00 output f/f (setting ?11? is prohibited.) inverts output upon match between tm00 and cr010. sets one-shot pulse output mode. 0/1 1 1 (d) prescaler mode register 00 (prm00) 0/1 0/1 0 1 prm00 prm001 prm000 selects count clock (setting ?11? is prohibited). specifies the rising edge for pulse width detection. 0/1 0/1 es110 es100 es010 es000 setting invalid (setting ?10? is prohibited.) 00 32 caution do not set 0000h to the cr000 and cr010 registers. www..net
chapter 6 16-bit timer/event counter 00 preliminary user?s manual u16898ej1v0ud 113 figure 6-35. timing of one-shot pulse output operation with external trigger (wit h rising edge specified) 0000h n nn n n mm m m m n + 1 n + 2 m + 1 m + 2 m ? 2m ? 1 0001h 0000h count clock tm00 count value cr010 set value cr000 set value ti000 pin input inttm010 inttm000 to00 pin output when tmc00 is set to 08h (tm00 count starts) t caution 16-bit timer counter 00 starts operating as soon as a value othe r than 00 (operation stop mode) is set to the tmc002 and tmc003 bits. remark n < m www..net
chapter 6 16-bit timer/event counter 00 preliminary user?s manual u16898ej1v0ud 114 6.5 cautions related to 16-bit timer/event counter 00 (1) timer start errors an error of up to one clock may occur in the time requir ed for a match signal to be generated after timer start. this is because 16-bit timer counter 00 (tm00) is started asynchronously to the count clock. figure 6-36. start timing of 16-bit timer counter 00 (tm00) tm00 count value 0000h 0001h 0002h 0004h count clock timer start 0003h (2) 16-bit timer capture/co mpare register setting set 16-bit timer capture/compare register 000 (cr000) to other than 0000h in the clear & start mode entered on match between tm00 and cr000. this means a 1-pulse count operation cannot be performed when this register is used as an external event counter. (3) capture register data retention the values of 16-bit timer capture/compare register s 000, 010 (cr000, cr010) after 16-bit timer/event counter 00 has stopped are not guaranteed. (4) valid edge setting set the valid edge of the ti000 pin after setting bits 2 and 3 (tmc002 and tmc003) of 16-bit timer mode control register 00 (tmc00) to 0, 0, respectively, and then stopping the timer operation. the valid edge is set by bits 4 and 5 (es000 and es010) of pr escaler mode register 00 (prm00). (5) re-triggering one-shot pulse (a) one-shot pulse output by software when a one-shot pulse is output, do not set the ospt00 bit to 1. do not output the one-shot pulse again until inttm000, which occurs upon a match with the cr 000 register, or inttm010, which occurs upon a match with the cr010 register, occurs. (b) one-shot pulse output with external trigger if the external trigger occurs again while a one-shot pulse is output, it is ignored. (c) one-shot pulse output function when using the one-shot pulse output of 16-bit timer/event counter 00 with a software trigger, do not change the level of the ti000 pin or its alternate function port pin. because the external trigger is valid even in this case , the timer is cleared and st arted even at the level of the ti000 pin or its alternate function port pin, resulting in the output of a pulse at an undesired timing. www..net
chapter 6 16-bit timer/event counter 00 preliminary user?s manual u16898ej1v0ud 115 (6) operation of ovf00 flag <1> the ovf00 flag is also set to 1 in the following case. either of the clear & start mode entered on a matc h between tm00 and cr000, clear & start at the valid edge of the ti000 pin, or fr ee-running mode is selected. cr000 is set to ffffh. when tm00 is counted up from ffffh to 0000h. figure 6-37. operation timing of ovf00 flag count clock cr000 tm00 ovf00 inttm000 ffffh fffeh ffffh 0000h 0001h <2> even if the ovf00 flag is cleared before the next count clock is counted (before tm00 becomes 0001h) after the occurrence of a tm00 overflow, the ov f00 flag is reset newly and clear is disabled. (7) conflicting operations <1> when the 16-bit timer capture/compare register ( cr000/cr010) is used as a compare register, if the write period and the match timing of 16-bit timer coun ter 00 (tm00) conflict, match determination is not successfully done. do not perform a write oper ation of cr000/cr010 near the match timing. when performing a write operation, refer to (11) changing compare regi ster during timer operation . <2> if the read period and capture trigger input conflic t when cr000/cr010 is used as a capture register, capture trigger input has priority. t he data read from cr000/cr010 is undefined. figure 6-38. capture regist er data retention timing count clock tm00 count value edge input inttm010 capture read signal cr010 capture value n n + 1 n + 2 m m + 1 m + 2 x n + 2 capture, but read value is not guaranteed capture m + 1 www..net
chapter 6 16-bit timer/event counter 00 preliminary user?s manual u16898ej1v0ud 116 (8) timer operation <1> even if 16-bit timer counter 00 (tm00) is read, the value is not captured by 16-bit timer capture/compare register 010 (cr010). <2> regardless of the cpu?s operation mode, when th e timer stops, the signals input to pins ti000/ti010 are not acknowledged. <3> one-shot pulse output normally o perates only in the free-running mode or in the clear & start mode at the valid edge of the ti000 pin. because an overflow does not occu r in the clear & start mode on a match between tm00 and cr000, one-shot pulse output is not possible. (9) capture operation <1> if the ti000 pin is specified as the valid edge of the count clock, a capture operation by the capture register specified as the trigger for the ti000 pin is not possible. <2> if both the rising and falling edges are selected as the valid edges of the ti000 pin, capture is not performed. <3> to ensure the reliability of the capture operation, the c apture trigger requires a pulse longer than two cycles of the count clock selected by prescaler mode register 00 (prm00). <4> the capture operation is perform ed at the fall of the count clock. a interrupt request input (inttm0n0), however, occurs at the rise of the next count clock. remark n = 0, 1 (10) compare operation the capture operation may not be per formed for cr000/cr010 set in compare mode even if a capture trigger is input. (11) changing compare regi ster during timer operation <1> when changing cr0n0 around the timing of a matc h between 16-bit timer counter 00 (tm00) and 16-bit timer capture/compare register 0n0 (cr0n0) during timer counting, the change timing may conflict with the timing of the match, so the o peration is not guaranteed in such cases. to change cr0n0 during timer counting, follow the procedure below using an inttm000 interrupt. 1. disable the timer output inversion operati on at the match between tm00 and cr000 (toc001 = 0). 2. disable the inttm000 interrupt (tmmk000 = 1). 3. rewrite cr000. 4. wait for 1 cycle of the tm00 count clock. 5. enable the timer output inversion operatio n at the match between tm00 and cr000 (toc001 = 1). 6. clear the interrupt req uest flag of inttm000 (tmif000 = 0). 7. enable the inttm000 interrupt (tmmk000 = 0). www..net
chapter 6 16-bit timer/event counter 00 preliminary user?s manual u16898ej1v0ud 117 1. disable the timer output inversion operati on at the match between tm00 and cr010 (toc004 = 0). 2. disable the inttm000 interrupt (tmmk000 = 1). 3. rewrite cr010. 4. wait for 1 cycle of the tm00 count clock. 5. enable the timer output inversion operatio n at the match between tm00 and cr010 (toc004 = 1). 6. clear the interrupt req uest flag of inttm000 (tmif000 = 0). 7. enable the inttm000 interrupt (tmmk000 = 0). while interrupts and timer output inversion are disabled (1 to 4 above), timer counting is continued. if the value to be set in cr0n0 is small, the value of tm00 may exceed cr0n0. therefore, set the value, considering the time lapse of the timer clock and cpu after an inttm000 interrupt has been generated. remark n = 0 or 1 <2> if cr010 is changed during timer counting without performing processing <1> above, the value in cr010 may be rewritten twice or more, causing an in version of the output leve l of the to00 pin at each rewrite. (12) edge detection <1> if the ti000 pin or the ti010 pin is high level i mmediately after system reset and the rising edge or both the rising and falling edges are specified as the valid edge for the ti000 pin or ti010 pin to enable 16-bit timer counter 00 (tm00) operation, a rising edge is detected immediatel y. be careful when pulling up the ti000 pin or the ti010 pin. however, the rising edge is not detected at restar t after the operation has been stopped once. <2> the sampling clock used to remove noise differs when a ti000 valid edge is used as the count clock and when it is used as a capture trigger. in the former case, the count clock is f xp , and in the latter case the count clock is selected by prescaler mode regist er 00 (prm00). the capture operation is not performed until the valid edge is sampled and the valid level is detected twice, thus elimin ating, noise with a short pulse width. (13) stop mode or system clock stop mode setting except when ti000, ti010 input is selected, stop t he timer operation before setting stop mode or system clock stop mode; otherwise the timer may ma lfunction when the system clock starts. www..net
preliminary user?s manual u16898ej1v0ud 118 chapter 7 8-bit timer 80 7.1 function of 8-bit timer 80 8-bit timer 80 has an 8-bit interval timer function and ge nerates an interrupt at intervals specified in advance. table 7-1. interval ti me of 8-bit timer 80 minimum interval time maximum interval time resolution 2 6 /f xp (8 s) 2 14 /f xp (2.05 ms) 2 6 /f xp (8 s) 2 8 /f xp (32 s) 2 16 /f xp (8.19 ms) 2 8 /f xp (32 s) 2 10 /f xp (128 s) 2 18 /f xp (32.7 ms) 2 10 /f xp (128 s) f xp = 8.0 mhz 2 16 /f xp (8.19 ms) 2 24 /f xp (2.01 s) 2 16 /f xp (8.19 ms) 2 6 /f xp (6.4 s) 2 14 /f xp (1.64 ms) 2 6 /f xp (6.4 s) 2 8 /f xp (25.6 s) 2 16 /f xp (6.55 ms) 2 8 /f xp (25.6 s) 2 10 /f xp (102 s) 2 18 /f xp (26.2 ms) 2 10 /f xp (102 s) f xp = 10.0 mhz 2 16 /f xp (6.55 ms) 2 24 /f xp (1.68 s) 2 16 /f xp (6.55 ms) remark f xp : oscillation frequency of clock to peripheral hardware www..net
chapter 7 8-bit timer 80 preliminary user?s manual u16898ej1v0ud 119 7.2 configuration of 8-bit timer 80 8-bit timer 80 consists of the following hardware. table 7-2. configuration of 8-bit timer 80 item configuration timer counter 8-bit timer counter 80 (tm80) register 8-bit compare register 80 (cr80) control register 8-bit timer mode control register 80 (tmc80) figure 7-1. block diag ram of 8-bit timer 80 internal bus internal bus 8-bit compare register 80 (cr80) match 8-bit timer/counter 80 (tm80) clear inttm80 f xp /2 6 f xp /2 16 tce80 tcl801 tcl800 8-bit timer mode control register 80 (tmc80) f xp /2 8 f xp /2 10 selector remark f xp : oscillation frequency of clock to peripheral hardware www..net
chapter 7 8-bit timer 80 preliminary user?s manual u16898ej1v0ud 120 (1) 8-bit compare register 80 (cr80) this 8-bit register always compares its set value with the count value of 8-bit timer/counter 80 (tm80). it generates an interrupt request signal (i nttm80) if the two values match. cr80 is set by using an 8-bit memory manipulation instruction. a value of 00h to ffh can be set to this register. reset input makes the contents of this register undefined. figure 7-2. format of 8-bit compare register 80 (cr80) symbol cr80 address: ffcdh after reset: undefined w 76543210 caution when changing the value of cr80, be sure to stop the timer operation. if the value of cr80 is changed with the timer ope ration enabled, a match inte rrupt request signal may be generated immediately. (2) 8-bit timer/counter 80 (tm80) this 8-bit register counts the count pulses. the value of tm80 can be read by using an 8-bit memory manipulation instruction. reset input clears tm80 to 00h. figure 7-3. format of 8-bit timer counter 80 (tm80) symbol tm80 address: ffceh after reset: 00h r 76543210 www..net
chapter 7 8-bit timer 80 preliminary user?s manual u16898ej1v0ud 121 7.3 register controlling 8-bit timer 80 8-bit timer 80 is controlled by 8-bit timer mode control register 80 (tmc80). (1) 8-bit timer mode control register 80 (tmc80) this register is used to enable or stop the operati on of 8-bit timer/counter 80 (tm80), and to set the count clock of tm80. this register is set by using a 1-bit or 8-bit memory manipulation instruction. reset input clears tmc80 to 00h. figure 7-4. format of 8-bit timer mode control register 80 (tmc80) address: ffcch after reset: 00h r/w symbol <7> 6 5 4 3 2 1 0 tmc80 tce80 0 0 0 0 tcl801 tcl800 0 tce80 control of operation of tm80 0 stop operation (clear tm80 to 00h). 1 enable operation. selection of count clock of 8-bit timer 80 tcl801 tcl800 f xp = 8.0 mhz f xp = 10.0 mhz 0 0 f xp /2 6 125 khz 156.3 khz 0 1 f xp /2 8 31.25 khz 39.06 khz 1 0 f xp /2 10 7.81 khz 9.77 khz 1 1 f xp /2 16 0.12 khz 0.15 khz caution be sure to set tmc80 a fter stopping the timer operation. remark f xp : oscillation frequency of clock to peripheral hardware www..net
chapter 7 8-bit timer 80 preliminary user?s manual u16898ej1v0ud 122 7.4 operation of 8-bit timer 80 7.4.1 operation as interval timer when 8-bit timer 80 operates as an interval timer, it can repeatedly generate an interrupt at intervals specified by the count value set in advance to 8-bit compare register 80 (cr80). to use 8-bit timer 80 as an interval timer, make the following setting. <1> disable the operation of 8-bit time r/counter 80 (clear tce80 (bit 7 of 8-bit timer mode control register 80 (tmc80)) to 0). <2> set the count clock of 8-bit timer 80 (refer to tables 7-3 and 7-4 ). <3> set the count value to cr80. <4> enable the operation of tm80 (set tce80 to 1). when the count value of 8-bit timer/counter 80 (tm80) matches the set value of cr80, the value of tm80 is cleared to 00h and counting is continued. at the same time, an interrupt request signal (inttm80) is generated. tables 7-3 and 7-4 show the interval time, and figure 7-5 shows the timing of the interval timer operation. cautions 1. when changing the value of cr80, be sure to stop the timer operation. if the value of cr80 is changed with the timer operation enabled, a matc h interrupt request si gnal may be generated immediately. 2. if the count clock of tmc80 is set and the operation of tm80 is enabled at the same time by using an 8-bit memory manipulation instructi on, the error of one cycle after the timer is started may be 1 clock or more. therefore, be sure to follow the ab ove sequence when using tm80 as an interval timer. table 7-3. interval time of 8-bit timer 80 (f xp = 8.0 mhz) tcl801 tcl800 minimum interval time maximum interval time resolution 0 0 2 6 /f xp (8 s) 2 14 /f xp (2.05 ms) 2 6 /f xp (8 s) 0 1 2 8 /f xp (32 s) 2 16 /f xp (8.19 ms) 2 8 /f xp (32 s) 1 0 2 10 /f xp (128 s) 2 18 /f xp (32.7 ms) 2 10 /f xp (128 s) 1 1 2 16 /f xp (8.19 ms) 2 24 /f xp (2.01 s) 2 16 /f xp (8.19 ms) remark f xp : oscillation frequency of clock to peripheral hardware table 7-4. interval time of 8-bit timer 80 (f xp = 10.0 mhz) tcl811 tcl810 minimum interval time maximum interval time resolution 0 0 2 6 /f xp (6.4 s) 2 14 /f xp (1.64 ms) 2 6 /f xp (6.4 s) 0 1 2 8 /f xp (25.6 s) 2 16 /f xp (6.55 ms) 2 8 /f xp (25.6 s) 1 0 2 10 /f xp (102 s) 2 18 /f xp (26.2 ms) 2 10 /f xp (102 s) 1 1 2 16 /f xp (6.55 ms) 2 24 /f xp (1.68 s) 2 16 /f xp (6.55 ms) remark f xp : oscillation frequency of clock to peripheral hardware www..net
chapter 7 8-bit timer 80 preliminary user?s manual u16898ej1v0ud 123 figure 7-5. timing of interval timer operation clear clear interrupt acknowledged interrupt acknowledged count start interval time interval time interval time count clock tm80 count value cr80 tce80 inttm80 to80 n 01h 00h n 01h 00h n 00h 01h nn nn t remark interval time = (n + 1) t: n = 00h to ffh www..net
chapter 7 8-bit timer 80 preliminary user?s manual u16898ej1v0ud 124 7.5 notes on 8-bit timer 80 (1) error when timer starts the time from starting the timer to gener ation of the match signal in cludes an error of up to 1.5 clocks. this is because, if the timer is started while the count clock is high, the rising edge may be immediately detected and the counter may be incremented (refer to figure 7-6 ). figure 7-6. case where error of 1.5 clocks (max.) occurs 8-bit timer counter 80 (tm80) count pulse clear signal selected clock tce80 delay a delay b selected clock tce80 clear signal count pulse tm80 count value 00h 01h 02h 03h c delay a delay b if the timer is started when the selected clock is high and if delay a > delay b, an error of up to 1.5 clocks occurs. (2) setting of 8-bit compare register 80 8-bit compare register 80 (cr80) can be set to 00h. (3) note on setting stop mode before executing the stop instruction, be sure to stop the timer operation (tce80 = 0). www..net
preliminary user?s manual u16898ej1v0ud 125 chapter 8 8-bit timer h1 8.1 functions of 8-bit timer h1 8-bit timer h1 has the following functions. ? interval timer ? pwm output mode ? square-wave output 8.2 configuration of 8-bit timer h1 8-bit timer h1 consists of the following hardware. table 8-1. configuration of 8-bit timer h1 item configuration timer register 8-bit timer counter h1 registers 8-bit timer h compare register 01 (cmp01) 8-bit timer h compare register 11 (cmp11) timer output toh1 control registers 8-bit timer h mode register 1 (tmhmd1) port mode register 4 (pm4) port register 4 (p4) figure 8-1 shows a block diagram. www..net
chapter 8 8-bit timer h1 preliminary user?s manual u16898ej1v0ud 126 figure 8-1. block diag ram of 8-bit timer h1 match selector internal bus tmhe1 cks12 cks11 cks10 tmmd11 tmmd10 tolev1 toen1 8-bit timer h mode register 1 (tmhmd1) 8-bit timer h compare register 11 (cmp11) decoder toh1/p42 inttmh1 selector f xp f xp /2 2 f xp /2 4 f xp /2 6 f xp /2 12 f rl /2 7 interrupt generator output controller level inversion 1 0 f/f r 8-bit timer counter h1 pwm mode signal timer h enable signal clear 3 2 8-bit timer h compare register 01 (cmp01) output latch (p42) pm42 www..net
chapter 8 8-bit timer h1 preliminary user?s manual u16898ej1v0ud 127 (1) 8-bit timer h compare register 01 (cmp01) this register can be read or written by an 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 8-2. format of 8-bit time r h compare register 01 (cmp01) symbol cmp01 address: ff0eh after reset: 00h r/w 7 6 5 4 32 1 0 caution cmp01 cannot be rewritte n during timer count operation. (2) 8-bit timer h compare register 11 (cmp11) this register can be read or written by an 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 8-3. format of 8-bit time r h compare register 11 (cmp11) symbol cmp11 address: ff0fh after reset: 00h r/w 7 6 5 4 32 1 0 cmp11 can be rewritten during timer count operation. if the cmp11 value is rewritten during timer operation, tr ansferring is performed at the timing at which the count value and cmp11 value match. if the transfer timing a nd writing from cpu to cmp11 conflict, transfer is not performed. caution in the pwm output mode, be sure to set cm p11 when starting the timer count operation (tmhe1 = 1) after the timer count operation was stopped (tmh e1 = 0) (be sure to set again even if setting the same value to cmp11). www..net
chapter 8 8-bit timer h1 preliminary user?s manual u16898ej1v0ud 128 8.3 registers control ling 8-bit timer h1 the following three registers are used to control 8-bit timer h1. ? 8-bit timer h mode register 1 (tmhmd1) ? port mode register 4 (pm4) ? port register 4 (p4) (1) 8-bit timer h mode register 1 (tmhmd1) this register controls the mode of timer h. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. www..net
chapter 8 8-bit timer h1 preliminary user?s manual u16898ej1v0ud 129 figure 8-4. format of 8-bit time r h mode register 1 (tmhmd1) tmhe1 stop timer count operation (counter is cleared to 0) enable timer count operation (count operation started by inputting clock) tmhe1 0 1 timer operation enable tmhmd1 symbol cks12 cks11 cks10 tmmd11 tmmd10 tolev1 toen1 address: ff70h after reset: 00h r/w f xp f xp /2 2 f xp /2 4 f xp /2 6 f xp /2 12 f rl /2 7 cks12 0 0 0 0 1 1 cks11 0 0 1 1 0 0 cks10 0 1 0 1 0 1 (10 mhz) (2.5 mhz) (625 khz) (156.25 khz) (2.44 khz) (1.88 khz (typ.)) count clock (f cnt ) selection setting prohibited other than above interval timer mode pwm output mode setting prohibited tmmd11 0 1 tmmd10 0 0 timer operation mode low level high level tolev1 0 1 timer output level control (in default mode) disable output enable output toen1 0 1 timer output control other than above <7> 6 5 4 3 2 <1> <0> cautions 1. when tmhe1 = 1, setting the other bits of the tmhmd1 register is prohibited. 2. in the pwm output mode, be sure to set 8- bit timer h compare register 11 (cmp11) when starting the timer count operation (tmhe1 = 1) after the timer count operation was stopped (tmhe1 = 0) (be sure to set again even if setting the same val ue to the cmp11 register). remarks 1. f xp : oscillation frequency of clock to peripheral hardware 2. f rl : low-speed ring-osc clock oscillation frequency 3. figures in parentheses apply to operation at f xp = 10 mhz, f rl = 240 khz (typ.). www..net
chapter 8 8-bit timer h1 preliminary user?s manual u16898ej1v0ud 130 (2) port mode register 4 (pm4) this register sets port 4 input/output in 1-bit units. when using the p42/toh1 pin for timer output, cl ear pm42 and the output latch of p42 to 0. pm4 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to ffh. figure 8-5. format of port mode register 4 (pm4) address: ff24h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm4 1 1 pm45 pm44 pm43 pm42 pm41 pm40 pm4n p4n pin i/o mode selection (n = 0 to 5) 0 output mode (output buffer on) 1 input mode (output buffer off) www..net
chapter 8 8-bit timer h1 preliminary user?s manual u16898ej1v0ud 131 8.4 operation of 8-bit timer h1 8.4.1 operation as interval timer/square-wave output when 8-bit timer counter h1 and compare register 01 (cmp01) match, an interrupt request signal (inttmh1) is generated and 8-bit timer counter h1 is cleared to 00h. compare register 11 (cmp11) is not used in interval timer mode. since a match of 8-bit timer counter h1 and the cmp11 register is not detected even if the cmp11 register is set, timer output is not affected. by setting bit 0 (toen1) of timer h mode register 1 (tmh md1) to 1, a square wave of any frequency (duty = 50%) is output from toh1. (1) usage generates the inttmh1 signal repeatedly at the same interval. <1> set each register. figure 8-6. register setting during inte rval timer/square-wave output operation (i) setting timer h mode register 1 (tmhmd1) 0 0/1 0/1 0/1 0 0 0/1 0/1 tmmd10 tolev1 toen1 cks11 cks12 tmhe1 tmhmd1 cks10 tmmd11 timer output setting timer output level inversion setting interval timer mode setting count clock (f cnt ) selection count operation stopped (ii) cmp01 register setting ? compare value (n) <2> count operation starts when tmhe1 = 1. <3> when the values of 8-bit timer counter h1 and the cmp01 register match, the inttmh1 signal is generated and 8-bit timer counter h1 is cleared to 00h. interval time = (n +1)/f cnt <4> subsequently, the inttmh1 signal is generated at the same interval. to stop the count operation, clear tmhe1 to 0. www..net
chapter 8 8-bit timer h1 preliminary user?s manual u16898ej1v0ud 132 (2) timing chart the timing of the interval timer/square- wave output operation is shown below. figure 8-7. timing of interval time r/square-wave output operation (1/2) (a) basic operation 00h count clock count start 8-bit timer counter h1 cmp01 tmhe1 inttmh1 toh1 01h n clear interval time clear n 00h 01h n 00h 01h 00h <2> level inversion, match interrupt occurrence, 8-bit timer counter h1 clear <2> level inversion, match interrupt occurrence, 8-bit timer counter h1 clear <3> <1> <1> the count operation is enabled by setting the tmhe1 bi t to 1. the count clock starts counting no more than 1 clock after the operation is enabled. <2> when the values of 8-bit timer counter h1 and the cmp01 register match, the value of 8-bit timer counter h1 is cleared, the toh1 output level is in verted, and the inttmh1 signal is output. <3> the inttmh1 signal and toh1 output become inactive by clearing the tmhe1 bit to 0 during timer h1 operation. if these are inactive from the first, the level is retained. remark n = 01h to feh www..net
chapter 8 8-bit timer h1 preliminary user?s manual u16898ej1v0ud 133 figure 8-7. timing of interval time r/square-wave output operation (2/2) (b) operation when cmp01 = ffh 00h count clock count start 8-bit timer counter h1 cmp01 tmhe1 inttmh1 toh1 01h feh clear clear ffh 00h feh ffh 00h ffh interval time (c) operation when cmp01 = 00h count clock count start 8-bit timer counter h1 cmp01 tmhe1 inttmh1 toh1 00h 00h interval time www..net
chapter 8 8-bit timer h1 preliminary user?s manual u16898ej1v0ud 134 8.4.2 operation as pwm output mode in pwm output mode, a pulse with an arbi trary duty and arbitrary cycle can be output. 8-bit timer compare register 01 (cmp01 ) controls the cycle of timer output (t oh1). rewriting the cmp01 register during timer operation is prohibited. 8-bit timer compare register 11 (cmp11) controls the dut y of timer output (toh1). re writing the cmp11 register during timer operation is possible. the operation in pwm output mode is as follows. toh1 output becomes active and 8-bit timer counter h1 is cleared to 0 when 8-bit timer counter h1 and the cmp01 register match after the timer count is started. toh1 output becomes inactive when 8-bit timer counter h1 and the cmp11 register match. (1) usage in pwm output mode, a pulse for which an arbitr ary duty and arbitrary cycle can be set is output. <1> set each register. figure 8-8. register setting in pwm output mode (i) setting timer h mode register 1 (tmhmd1) 0 0/1 0/1 0/1 1 0 0/1 1 tmmd10 tolev1 toen1 cks11 cks12 tmhe1 tmhmd1 cks10 tmmd11 timer output enabled timer output level inversion setting pwm output mode selection count clock (f cnt ) selection count operation stopped (ii) setting cmp01 register ? compare value (n): cycle setting (iii) setting cmp11 register ? compare value (m): duty setting remark 00h cmp11 (m) < cmp01 (n) ffh <2> the count operation starts when tmhe1 = 1. <3> the cmp01 register is the compare register that is to be compared firs t after count operation is enabled. when the values of 8-bit timer counter h1 and the cmp0 1 register match, 8-bit timer counter h1 is cleared, an interrupt request signal (inttmh1) is generated, a nd toh1 output becomes active. at the same time, the compare register to be compared with 8-bit timer c ounter h1 is changed from the cmp01 register to the cmp11 register. www..net
chapter 8 8-bit timer h1 preliminary user?s manual u16898ej1v0ud 135 <4> when 8-bit timer counter h1 and the cmp11 regist er match, toh1 output bec omes inactive and the compare register to be compared with 8-bit timer coun ter h1 is changed from the cmp11 register to the cmp01 register. at this time, 8-bit timer counter h1 is not cleared and the inttmh1 signal is not generated. <5> by performing procedures <3> and <4> repeatedl y, a pulse with an arbitrary duty can be obtained. <6> to stop the count operation, set tmhe1 = 0. if the setting value of the cmp01 register is n, the setting value of the cmp11 register is m, and the count clock frequency is f cnt , the pwm pulse output cycle and duty are as follows. pwm pulse output cycle = (n+1)/f cnt duty = active width : total widt h of pwm = (m + 1) : (n + 1) cautions 1. in pwm output mode, three operation clocks (signal selected using the cks12 to cks10 bits of the tmhmd1 register) are required to transfer the cmp11 register value after rewriting the register. 2. be sure to set th e cmp11 register when starting the ti mer count operation (tmhe1 = 1) after the timer count operation was stopped (tmhe1 = 0) (be sure to set again even if setting the same value to the cmp11 register). www..net
chapter 8 8-bit timer h1 preliminary user?s manual u16898ej1v0ud 136 (2) timing chart the operation timing in pwm output mode is shown below. caution make sure that the cmp11 register setting value (m) and cmp01 register setting value (n) are within the following range. 00h cmp11 (m) < cmp01 (n) ffh figure 8-9. operation timing in pwm output mode (1/4) (a) basic operation count clock 8-bit timer counter h1 cmp01 tmhe1 inttmh1 toh1 (tolev1 = 0) toh1 (tolev1 = 1) 00h 01h a5h 00h 01h 02h a5h 00h a5h 00h 01h 02h cmp11 a5h 01h <1> <2> <3> <4> <1> the count operation is enabled by setting the tmhe1 bit to 1. start 8-bit timer counter h1 by masking one count clock to count up. at this time, toh1 output remains inactive (when tolev1 = 0). <2> when the values of 8-bit timer counter h1 and the cmp0 1 register match, the toh1 output level is inverted, the value of 8-bit timer counter h1 is cleared, and the inttmh1 signal is output. <3> when the values of 8-bit timer counter h1 and the cm p11 register match, the le vel of the toh1 output is returned. at this time, the 8-bit timer counter val ue is not cleared and the inttmh1 signal is not output. <4> clearing the tmhe1 bit to 0 during timer h1 operati on makes the inttmh1 signal and toh1 output inactive. www..net
chapter 8 8-bit timer h1 preliminary user?s manual u16898ej1v0ud 137 figure 8-9. operation timing in pwm output mode (2/4) (b) operation when cm p01 = ffh, cmp11 = 00h count clock 8-bit timer counter h1 cmp01 tmhe1 inttmh1 toh1 (tolev1 = 0) 00h 01h ffh 00h 01h 02h ffh 00h ffh 00h 01h 02h cmp11 ffh 00h (c) operation when cmp01 = ffh, cmp11 = feh count clock 8-bit timer counter h1 cmp01 tmhe1 inttmh1 toh1 (tolev1 = 0) 00h 01h feh ffh 00h 01h feh ffh 00h 01h feh ffh 00h cmp11 ffh feh www..net
chapter 8 8-bit timer h1 preliminary user?s manual u16898ej1v0ud 138 figure 8-9. operation timing in pwm output mode (3/4) (d) operation when cmp01 = 01h, cmp11 = 00h count clock 8-bit timer counter h1 cmp01 tmhe1 inttmh1 toh1 (tolev1 = 0) 01h 00h 01h 00h 01h 00h 00h 01h 00h 01h cmp11 00h www..net
chapter 8 8-bit timer h1 preliminary user?s manual u16898ej1v0ud 139 figure 8-9. operation timing in pwm output mode (4/4) (e) operation by changing cmp11 (cmp11 = 01h 03h, cmp01 = a5h) count clock 8-bit timer counter h1 cmp01 tmhe1 inttmh1 toh1 (tolev1 = 0) 00h 01h 02h a5h 00h 01h 02h 03h a5h 00h 01h 02h 03h a5h 00h cmp11 01h a5h 03h 01h (03h) <1> <3> <4> <2> <2>' <5> <6> <1> the count operation is enabled by setting tmhe1 = 1. start 8-bit timer counter h1 by masking one count clock to count up. at this time, the toh1 output remains inactive (when tolev1 = 0). <2> the cmp11 register value can be changed during time r counter operation. this operation is asynchronous to the count clock. <3> when the values of 8-bit timer counter h1 and the cmp01 register match, the value of 8-bit timer counter h1 is cleared, the toh1 output becomes active, and the inttmh1 signal is output. <4> if the cmp11 register value is changed, the value is latched and not transferred to the register. when the values of 8-bit timer counter h1 and the cmp11 register before the change match, the value is transferred to the cmp11 register and the cmp11 re gister value is changed (<2>?). however, three count clocks or more are required fr om when the cmp11 register value is changed to when the value is transferred to the register. if a match si gnal is generated within thr ee count clocks, the changed value cannot be transferred to the register. <5> when the values of 8-bit timer counter h1 and the cm p11 register after the change match, the toh1 output becomes inactive. 8-bit timer counter h1 is no t cleared and the inttmh1 signal is not generated. <6> clearing the tmhe1 bit to 0 during timer h1 operati on makes the inttmh1 signal and toh1 output inactive. www..net
preliminary user?s manual u16898ej1v0ud 140 chapter 9 watchdog timer 9.1 functions of watchdog timer the watchdog timer is used to detect an inadvertent program loop. if a program loop is detected, an internal reset signal is generated. when a reset occurs due to the watchdog timer, bit 4 (wdtrf) of the reset control flag register (resf) is set to 1. for details of resf, see chapter 14 reset function . table 9-1. loop detection time of watchdog timer loop detection time during low-speed ring-osc clock op eration during operation of cl ock to peripheral hardware f rl /2 11 (8.53 ms) f xp /2 13 (819.2 s) f rl /2 12 (17.07 ms) f xp /2 14 (1.64 ms) f rl /2 13 (34.13 ms) f xp /2 15 (3.28 ms) f rl /2 14 (68.27 ms) f xp /2 16 (6.55 ms) f rl /2 15 (136.53 ms) f xp /2 17 (13.11 ms) f rl /2 16 (273.07 ms) f xp /2 18 (26.21 ms) f rl /2 17 (546.13 ms) f xp /2 19 (52.43 ms) f rl /2 18 (1.09 s) f xp /2 20 (104.86 ms) remarks 1. f rl : low-speed ring-osc clock oscillation frequency 2. f xp : oscillation frequency of clock to peripheral hardware 3. figures in parentheses apply to operation at f rl = 240 khz (typ.), f xp = 10 mhz. the operation mode of the watchdog time r (wdt) is switched according to the option byte setting of the on-chip low-speed ring-osc oscillator as shown in table 9-2. www..net
chapter 9 watchdog timer preliminary user?s manual u16898ej1v0ud 141 table 9-2. option byte setting an d watchdog timer operation mode option byte setting low-speed ring-osc cannot be stopped low-speed ring-osc can be stopped by software watchdog timer clock source fixed to f rl note 1 . ? selectable by software (f xp , f rl or stopped) ? when reset is released: f rl operation after reset operation star ts with the maximum interval (f rl /2 18 ). operation starts with the maximum interval (f rl /2 18 ). operation mode selection the interval can be changed only once. the clock selection/interval can be changed only once. features the watchdog timer cannot be stopped. the watchdog timer can be stopped note 2 . notes 1. as long as power is being supplied, low-speed ring- osc oscillation cannot be stopped (except in the reset period). 2. the conditions under which clock supply to t he watchdog timer is stopped differ depending on the clock source of the watchdog timer. <1> if the clock source is f xp , clock supply to the watchdog timer is stopped under the following conditions. ? when f xp is stopped ? in halt/stop mode ? during oscillation stabilization time <2> if the clock source is f rl , clock supply to the watchdog timer is stopped under the following conditions. ? if the cpu clock is f xp and if f rl is stopped by software befor e execution of the stop instruction ? in halt/stop mode remarks 1. f rl : low-speed ring-osc clock oscillation frequency 2. f xp : oscillation frequency of clock to peripheral hardware www..net
chapter 9 watchdog timer preliminary user?s manual u16898ej1v0ud 142 9.2 configuration of watchdog timer the watchdog timer consists of the following hardware. table 9-3. configuration of watchdog timer item configuration control registers watchdog timer mode register (wdtm) watchdog timer enable register (wdte) figure 9-1. block diagram of watchdog timer f rl /2 2 clock input controller output controller internal reset signal wdcs2 internal bus wdcs1 wdcs0 f xp /2 4 wdcs3 wdcs4 01 1 selector 16-bit counter or f xp /2 13 to f xp /2 20 f rl /2 11 to f rl /2 18 watchdog timer enable register (wdte) watchdog timer mode register (wdtm) 3 3 2 clear option byte (to set ?low-speed ring-osc cannot be stopped? or ?low-speed ring-osc can be stopped by software?) www..net
chapter 9 watchdog timer preliminary user?s manual u16898ej1v0ud 143 9.3 registers controlling watchdog timer the watchdog timer is controlled by the following two registers. ? watchdog timer mode register (wdtm) ? watchdog timer enable register (wdte) (1) watchdog timer mode register (wdtm) this register sets the overflow time and operation clock of the watchdog timer. this register can be set by an 8-bit memory manipula tion instruction and can be read many times, but can be written only once after reset is released. reset input sets this register to 67h. figure 9-2. format of watchdog timer mode register (wdtm) 0 wdcs0 1 wdcs1 2 wdcs2 3 wdcs3 4 wdcs4 5 1 6 1 7 0 symbol wdtm address: ff48h after reset: 67h r/w wdcs4 note 1 wdcs3 note 1 operation clock selection 0 0 low-speed ring-osc clock (f rl ) 0 1 clock to peripheral hardware (f xp ) 1 watchdog timer operation stopped overflow time setting wdcs2 note 2 wdcs1 note 2 wdcs0 note 2 during low-speed ring-osc clock operation during operation of clock to peripheral hardware 0 0 0 f rl /2 11 (8.53 ms) f xp /2 13 (819.2 s) 0 0 1 f rl /2 12 (17.07 ms) f xp /2 14 (1.64 ms) 0 1 0 f rl /2 13 (34.13 ms) f xp /2 15 (3.28 ms) 0 1 1 f rl /2 14 (68.27 ms) f xp /2 16 (6.55 ms) 1 0 0 f rl /2 15 (136.53 ms) f xp /2 17 (13.11 ms) 1 0 1 f rl /2 16 (273.07 ms) f xp /2 18 (26.21 ms) 1 1 0 f rl /2 17 (546.13 ms) f xp /2 19 (52.43 ms) 1 1 1 f rl /2 18 (1.09 s) f xp /2 20 (104.86 ms) notes 1. if ?low-speed ring-osc cannot be stopped? is specif ied by the option byte, this cannot be set. the low-speed ring-osc clock will be selected no matter what value is written. 2. reset is released at the maximu m cycle (wdcs2, 1, 0 = 1, 1, 1). www..net
chapter 9 watchdog timer preliminary user?s manual u16898ej1v0ud 144 cautions 1. set bits 7, 6, and 5 to 0, 1, and 1, respectively (when ?low -speed ring-osc cannot be stopped? is selected by the opti on byte, other values are ignored). 2. after reset is released, wdtm can be written only once by an 8-bit memory manipulation instruction. if writing is attempted a second time , an internal reset signal is generated. 3. wdtm cannot be set by a 1-bi t memory manipulation instruction. remarks 1. f rl : low-speed ring-osc clock oscillation frequency 2. f xp : oscillation frequency of clock to peripheral hardware 3. : don?t care 4. figures in parentheses apply to operation at f rl = 240 khz (typ.), f xp = 10 mhz. (2) watchdog timer enable register (wdte) writing ach to wdte clears the watchdog timer counter and starts counting again. this register can be set by an 8-bit memory manipulation instruction. reset input sets this register to 9ah. figure 9-3. format of watchdog timer enable register (wdte) 0 1 2 3 4 5 6 7 symbol wdte address: ff49h after reset: 9ah r/w cautions 1. if a value other than ach is written to wdte, an internal reset signal is generated. 2. if a 1-bit memory manipulation instruct ion is executed for wdte, an internal reset signal is generated. 3. the value read from wd te is 9ah (this differs from the written value (ach)). www..net
chapter 9 watchdog timer preliminary user?s manual u16898ej1v0ud 145 9.4 operation of watchdog timer 9.4.1 watchdog timer operation when ?low-speed ring-os c cannot be stopped? is selected by option byte the operation clock of watchdog timer is fixed to low-speed ring-osc. after reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (wdcs2, w dcs1, wdcs0) of the watchdog timer mode register (wdtm) = 1, 1, 1) . the watchdog timer operation cannot be stopped. the following shows the watchdog timer operation after reset release. 1. the status after reset release is as follows. ? operation clock: low-speed ring-osc clock ? cycle: f rl /2 18 (1.09 seconds: at operation with f rl = 240 khz (typ.)) ? counting starts 2. the following should be set in the watchdog timer mode register (wdtm) by an 8-bit memory manipulation instruction notes 1, 2 . ? cycle: set using bits 2 to 0 (wdcs2 to wdcs0) 3. after the above procedures are exec uted, writing ach to wdte clears the count to 0, enabling recounting. notes 1. the operation clock (low-speed ring-osc clock) cannot be changed. if any value is written to bits 3 and 4 (wdcs3, wdcs4) of wdtm, it is ignored. 2. as soon as wdtm is written, the c ounter of the watchdog timer is cleared. caution in this mode, ope ration of the watchdog timer cannot be stopped even during stop instruction execution. for 8-bit timer h1 (tmh1), a division of the lo w-speed ring-osc clock can be selected as the count source, so clear the watchdog timer using th e interrupt request of tmh1 before the watchdog timer overfl ows after stop instruction executi on. if this processing is not performed, an internal reset si gnal is generated when the watc hdog timer overflows after stop instruction execution. a status transition diagram is shown below www..net
chapter 9 watchdog timer preliminary user?s manual u16898ej1v0ud 146 figure 9-4. status transition diagram when ?low-speed ring-osc cannot be stopped? is selected by option byte reset wdt clock: f rl overflow time: 1.09 s (typ.) stop wdt count continues. halt wdt count continues. stop instruction halt instruction wdt clock is fixed to f rl . select overflow time (settable only once). wdt clock: f rl overflow time: 8.53 ms to 1.09 s (typ.) wdt count continues. interrupt interrupt wdte = ?ach? clear wdt counter. www..net
chapter 9 watchdog timer preliminary user?s manual u16898ej1v0ud 147 9.4.2 watchdog timer operation when ?low-speed ring- osc can be stopped by software? is selected by option byte the operation clock of the watchdog timer can be selected as either the low-speed ring-osc clock or the clock to peripheral hardware. after reset is released, operation is started at the maxi mum cycle of the low-speed ring-osc clock (bits 2, 1, and 0 (wdcs2, wdcs1, wdcs0) of the watchdog ti mer mode register (wdtm) = 1, 1, 1). the following shows the watchdog timer operation after reset release. 1. the status after reset release is as follows. ? operation clock: low-speed ring-osc clock ? cycle: f rl /2 18 (1.09 seconds: at operation with f rl = 240 khz (typ.)) ? counting starts 2. the following should be set in the watchdog timer mode register (wdtm) by an 8-bit memory manipulation instruction notes 1, 2, 3 . ? operation clock: any of the following can be selected using bits 3 and 4 (wdcs3 and wdcs4). low-speed ring-osc clock (f rl ) clock to peripheral hardware (f xp ) watchdog timer operation stopped ? cycle: set using bits 2 to 0 (wdcs2 to wdcs0) 3. after the above procedures are exec uted, writing ach to wdte clears the count to 0, enabling recounting. notes 1. as soon as wdtm is written, the count er of the watchdog timer is cleared. 2. set bits 7, 6, and 5 to 0, 1, 1, res pectively. do not set the other values. 3. if the watchdog timer is stopped by setting wdcs4 and wdcs3 to 1 and , respectively, an internal reset signal is not generated even if the following processing is performed. ? wdtm is written a second time. ? a 1-bit memory manipulation instruction is executed to wdte. ? a value other than ach is written to wdte. caution in this mode, watchdog ti mer operation is stopped during hal t/stop instruction execution. after halt/stop mode is released, counting is started agai n using the operation clock of the watchdog timer set before halt/stop instruction execution by wdtm. at this time, the counter is not cleared to 0 but holds its value. for the watchdog timer operation during stop mode and halt mode in each status, see 9.4.3 watchdog timer operation in stop mode and 9.4.4 watchdog timer operation in halt mode . a status transition diagram is shown below. www..net
chapter 9 watchdog timer preliminary user?s manual u16898ej1v0ud 148 figure 9-5. status transition diagram when ? low-speed ring-osc can be stopped by software? is selected by option byte reset wdt clock: f rl overflow time: 1.09 s (typ.) wdt clock = f rl select overflow time (settable only once). wdt clock: f rl overflow time: 8.53 ms to 1.09 s (typ.) wdt count continues. stop wdt count stops. halt wdt count stops. stop instruction halt instruction interrupt interrupt wdte = ?ach? clear wdt counter. wdt operation stops. wdcs4 = 1 wdt clock: f xp overflow time: f xp /2 13 to f xp /2 20 wdt count continues. wdt clock = f xp select overflow time (settable only once). wdt clock: f rl wdt count stops. wdte = ?ach? clear wdt counter. lsrstop = 1 lsrstop = 0 stop wdt count stops. halt wdt count stops. stop instruction halt instruction interrupt interrupt stop instruction interrupt interrupt halt instruction wdte = ?ach? clear wdt counter. www..net
chapter 9 watchdog timer preliminary user?s manual u16898ej1v0ud 149 9.4.3 watchdog timer operation in stop mode (when ?low-speed ring-osc can be stopped by software? is selected by option byte) the watchdog timer stops counting during stop instruction execution regardless of whether the clock to peripheral hardware or low-speed ring-osc clock is being used. (1) when the watchdog timer operation clock is the clock to peripheral hardware (f xp ) when the stop instruction is executed when stop instruction is executed, o peration of the watchdog timer is stopp ed. after stop mode is released, operation stops for 8 clocks of the low-speed ring-osc clo ck (after waiting for the oscillation stabilization time set by the oscillation stabilization time select register (ost s) after operation stops in the case of crystal/ceramic oscillation) and then counting is start ed again using the operation clock before the operation was stopped. at this time, the counter is not cleared to 0 but holds its value. figure 9-6. operation in stop mode (wdt op eration clock: clock to peripheral hardware) <1> cpu clock: crystal/ ceramic oscillation clock operation stopped operating oscillation stabilization time normal operation stop oscillation stabilization time (set by osts register) oscillation stopped watchdog timer operating f cpu cpu operation normal operation operation stopped (8/f rl ) <2> cpu clock: high-speed ring-os c clock or external clock input operation stopped operating normal operation oscillation stopped watchdog timer f cpu cpu operation stop operating normal operation operation stopped (8/f rl ) www..net
chapter 9 watchdog timer preliminary user?s manual u16898ej1v0ud 150 (2) when the watchdog timer operation clo ck is the low-speed ring-osc clock (f rl ) when the stop instruction is executed when the stop instruction is execut ed, operation of the watchdog timer is stopped. after stop mode is released, operation stops for 8 clocks of the low-speed ri ng-osc clock and then counting is started again using the operation clock before the operation was stopped. at this time, the counter is not cleared to 0 but holds its value. figure 9-7. operation in stop mode (wdt operation clock: low-s peed ring-osc clock) <1> cpu clock: crystal/ ceramic oscillation clock operating oscillation stabilization time normal operation oscillation stabilization time (set by osts register) watchdog timer operation stopped operating f rl f cpu cpu operation normal operation stop oscillation stopped operation stopped (8/f rl ) <2> cpu clock: high-speed ring-os c clock or external clock input operating normal operation watchdog timer operation stopped operating f rl f cpu cpu operation normal operation stop oscillation stopped operation stopped (8/f rl ) www..net
chapter 9 watchdog timer preliminary user?s manual u16898ej1v0ud 151 9.4.4 watchdog timer operation in halt mode (when ?low-speed ring-osc can be stopped by software? is selected by option byte) the watchdog timer stops counting during halt instruction execution regardles s of whether the operation clock of the watchdog timer is the clock to peripheral hardware (f xp ) or low-speed ring-osc clock (f rl ). after halt mode is released, counting is started again using the operation clo ck before the operation was stopped. at this time, the counter is not cleared to 0 but holds its value. figure 9-8. operation in halt mode watchdog timer operating f xp or f rl f cpu cpu operation normal operation operating halt operation stopped normal operation www..net
preliminary user?s manual u16898ej1v0ud 152 chapter 10 a/d converter 10.1 functions of a/d converter the a/d converter converts an analog input signal into a digital value, and consis ts of up to four channels (ani0 to ani3) with a resolution of 10 bits. the a/d converter has the following function. ? 10-bit resolution a/d conversion 10-bit resolution a/d conversion is carried out repeatedly for one channel selected from analog inputs ani0 to ani3. each time an a/d conversion operation en ds, an interrupt request (intad) is generated. figure 10-1 shows the timing of sampling and a/d conv ersion, and table 10-1 shows the sampling time and a/d conversion time. figure 10-1. timing of a/d con verter sampling and a/d conversion adcs conversion time conversion time sampling time sampling timing intad adcs 1 or ads rewrite sampling time www..net
chapter 10 a/d converter preliminary user?s manual u16898ej1v0ud 153 table 10-1. sampling time and a/d conversion time f xp = 8 mhz f xp = 10 mhz fr2 fr1 fr0 sampling time note 1 conversion time note 2 sampling time note 1 conversion time note 2 sampling time note 1 conversion time note 2 0 0 0 12/f xp 36/f xp 1.5 s 4.5 s 1.2 s 3.6 s 0 0 1 24/f xp 48/f xp 3.0 s 6.0 s 2.4 s 4.8 s 0 1 0 48/f xp 72/f xp 6.0 s 9.0 s 4.8 s 7.2 s 0 1 1 88/f xp 112/f xp 11.0 s 14.0 s 8.8 s 11.2 s 1 0 0 24/f xp 72/f xp 3.0 s 9.0 s 2.4 s 7.2 s 1 0 1 48/f xp 96/f xp 6.0 s 12.0 s 4.8 s 9.6 s 1 1 0 96/f xp 144/f xp 12.0 s 18.0 s 9.6 s 14.4 s 1 1 1 176/f xp 224/f xp 22.0 s 28.0 s 17.2 s 22.4 s notes 1. set the sampling time as follows. ? av ref 4.5 v: 1.0 s or more ? av ref 4.0 v: 2.4 s or more ? av ref 2.85 v: 3.0 s or more ? av ref 2.7 v: 11.0 s or more 2. set the a/d conversion time as follows. ? av ref 4.5 v: 3.0 s or more and less than 100 s ? av ref 4.0 v: 4.8 s or more and less than 100 s ? av ref 2.85 v: 6.0 s or more and less than 100 s ? av ref 2.7 v: 14.0 s or more and less than 100 s remark f xp : oscillation frequency of clock to peripheral hardware www..net
chapter 10 a/d converter preliminary user?s manual u16898ej1v0ud 154 figure 10-2 shows the block diagram of a/d converter. figure 10-2. block diag ram of a/d converter av ref v ss intad adcs bit 2 ads1 ads0 sample & hold circuit v ss voltage comparator controller a/d conversion result register (adcr, adcrh) analog input channel specification register (ads) a/d converter mode register (adm) internal bus successive approximation register (sar) ani0/p20 ani1/p21 ani2/p22 ani3/p23 adcs fr2 fr1 adce fr0 selector tap selector caution in the 78k0s/ka1+, v ss and av ss are internally connected. be sure to connect v ss to a stable gnd, and stabilize v ss via gnd (= 0 v). www..net
chapter 10 a/d converter preliminary user?s manual u16898ej1v0ud 155 10.2 configuration of a/d converter the a/d converter consists of the following hardware. table 10-2. registers of a/ d converter used on software item configuration registers successive approximat ion register (sar) 10-bit a/d conversion resu lt register (adcr) 8-bit a/d conversion result register (adcrh) a/d converter mode register (adm) analog input channel specification register (ads) port mode control register 2 (pmc2) port mode register 2 (pm2) (1) ani0 to ani3 pins these are the analog input pins of the 4- channel a/d converter. they input analog signals to be converted into digital signals. pins other than the one selected as the analog input pin by the analog input channel specification register (ads) can be used as input port pins. (2) sample & hold circuit the sample & hold circuit samples the input signal of the analog input pin selected by the selector when a/d conversion is started, and holds the sampled anal og input voltage value during a/d conversion. (3) series resistor string the series resistor string is connected between av ref and v ss , and generates a voltage to be compared with the analog input signal. figure 10-3. circuit configuration of series resistor string av ref v ss p-ch series resistor string adcs (4) voltage comparator the voltage comparator compar es the sampled analog input voltage and t he output voltage of the series resistor string. (5) successive approximation register (sar) this register compares the sampled analog voltage and the voltage of the series resistor string, and converts the result, starting from the most significant bit (msb). when the voltage value is converted into a digital valu e down to the least significant bit (lsb) (end of a/d conversion), the contents of the sar register are transfe rred to the a/d conversion result register (adcr). www..net
chapter 10 a/d converter preliminary user?s manual u16898ej1v0ud 156 (6) 10-bit a/d conversion r esult register (adcr) the result of a/d conversion is loaded from the successi ve approximation register to this register each time a/d conversion is completed, and the adcr regi ster holds the result of a/d conversi on in its lower 10 bits (the higher 6 bits are fixed to 0). (7) 8-bit a/d conversion result register (adcrh) the result of a/d conversion is loaded from the successi ve approximation register to this register each time a/d conversion is completed, and the adcrh register holds th e result of a/d conversion in its higher 8 bits. (8) controller when a/d conversion has been comp leted, intad is generated. (9) av ref pin this pin inputs an analog power/reference voltage to the a/d converter. when the a/ d converter is not used, connect this pin to v dd . the signal input to ani0 to ani3 is converted into a digital signal, based on the voltage applied across av ref and v ss . in the standby mode, the current flowi ng through the series resistor string can be reduced by lowering the voltage input to the av ref pin to the v ss level. (10) v ss pin this is the ground potential pin. caution in the 78k0s/ka1+, v ss and av ss are internally connected. be sure to connect v ss to a stable gnd, and stabilize v ss via gnd (= 0 v). (11) a/d converter mode register (adm) this register is used to set the conversion time of the analog input signal to be conver ted, and to start or stop the conversion operation. (12) analog input channel sp ecification register (ads) this register is used to specify the port that inputs the analog voltage to be converted into a digital signal. (13) port mode control register 2 (pmc2) this register is used when the p20/ani0 to p23/ani3 pins are used as the analog input pi ns of the a/d converter. www..net
chapter 10 a/d converter preliminary user?s manual u16898ej1v0ud 157 10.3 registers used by a/d converter the a/d converter uses the following six registers. ? a/d converter mode register (adm) ? analog input channel specification register (ads) ? 10-bit a/d conversion result register (adcr) ? 8-bit a/d conversion result register (adcrh) ? port mode control register 2 (pmc2) ? port mode register 2 (pm2) www..net
chapter 10 a/d converter preliminary user?s manual u16898ej1v0ud 158 (1) a/d converter mode register (adm) this register sets the conversion time for analog inpu t to be a/d converted, and starts/stops conversion. adm can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 10-4. format of a/d converter mode register (adm) address: ff80h after reset: 00h r/w symbol <7> 6 5 4 3 2 1 <0> adm adcs 0 fr2 fr1 fr0 0 0 adce adcs a/d conversion operation control 0 stops conversion operation 1 enables conversion operation f xp = 8 mhz f xp = 10 mhz fr2 fr1 fr0 sampling time note 1 conversion time note 2 sampling time note 1 conversion time note 2 sampling time note 1 conversion time note 2 0 0 0 12/f xp 36/f xp 1.5 s 4.5 s 1.2 s 3.6 s 0 0 1 24/f xp 48/f xp 3.0 s 6.0 s 2.4 s 4.8 s 0 1 0 48/f xp 72/f xp 6.0 s 9.0 s 4.8 s 7.2 s 0 1 1 88/f xp 112/f xp 11.0 s 14.0 s 8.8 s 11.2 s 1 0 0 24/f xp 72/f xp 3.0 s 9.0 s 2.4 s 7.2 s 1 0 1 48/f xp 96/f xp 6.0 s 12.0 s 4.8 s 9.6 s 1 1 0 96/f xp 144/f xp 12.0 s 18.0 s 9.6 s 14.4 s 1 1 1 176/f xp 224/f xp 22.0 s 28.0 s 17.2 s 22.4 s adce boost reference voltage generator operation control note 3 0 stops operation of reference voltage generator 1 enables operation of reference voltage generator notes 1. set the sampling time as follows. ? av ref 4.5 v: 1.0 s or more ? av ref 4.0 v: 2.4 s or more ? av ref 2.85 v: 3.0 s or more ? av ref 2.7 v: 11.0 s or more 2. set the a/d conversion time as follows. ? av ref 4.5 v: 3.0 s or more and less than 100 s ? av ref 4.0 v: 4.8 s or more and less than 100 s ? av ref 2.85 v: 6.0 s or more and less than 100 s ? av ref 2.7 v: 14.0 s or more and less than 100 s 3. a booster circuit is incorporated to realize low-vo ltage operation. the operat ion of the circuit that generates the reference voltage for boosting is controlled by adce, and it takes 1 s from operation start to operation stabilization. t herefore, when adcs is set to 1 after 1 s or more has elapsed from the time adce is set to 1, the conversion result at that time has priority over the first conversion result. www..net
chapter 10 a/d converter preliminary user?s manual u16898ej1v0ud 159 table 10-3. settings of adcs and adce adcs adce a/d co nversion operation 0 0 stop status (dc power consumption path does not exist) 0 1 conversion waiting mode (only reference voltage generator consumes power) 1 0 conversion mode (reference voltage generator operation stopped note ) 1 1 conversion mode (reference voltage generator operates) note data of first conversion cannot be used. figure 10-5. timing chart when boost reference voltage generator is used adce boost reference voltage adcs conversion operation conversion operation conversion stopped conversion waiting boost reference voltage generator: operating note note the time from the rising of the adce bit to the rising of the adcs bit must be 1 s or longer to stabilize the reference voltage. caution a/d conversion must be stoppe d before rewriting bits fr0 to fr2. remark f xp : oscillation frequency of clock to peripheral hardware www..net
chapter 10 a/d converter preliminary user?s manual u16898ej1v0ud 160 (2) analog input channel specification register (ads) this register specifies the input port of the analog voltage to be a/d converted. ads can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 10-6. format of analog input channel specification register (ads) ads0 ads1 0 0 0 0 0 0 analog input channel specification ani0 ani1 ani2 ani3 ads0 0 1 0 1 ads1 0 0 1 1 0 1 2 3 4 5 6 7 ads address: ff81h after reset: 00h r/w symbol caution be sure to clear bits 2 to 7 of ads to 0. (3) 10-bit a/d conversion r esult register (adcr) this register is a 16-bit register that stores the a/d conver sion result. the higher six bits are fixed to 0. each time a/d conversion ends, the conversion result is load ed from the successive approximation register, and is stored in adcr in order starting from bit 1 of ff19h. ff1 9h indicates the higher 2 bits of the conversion result, and ff18h indicates the lower 8 bits of the conversion result. adcr can be read by a 16-bit memory manipulation instruction. reset input makes adcr undefined. figure 10-7. format of 10-bit a/d conversion result register (adcr) symbol address: ff18h, ff19h after reset: undefined r ff19h ff18h 0 0 0 0 0 0 adcr caution when writing to the a/d converter mode re gister (adm) and analog i nput channel specification register (ads), the contents of adcr may beco me undefined. read the conversion result following conversion completion before writing to adm and ads. using timing other than the above may cause an incorrect c onversion result to be read. www..net
chapter 10 a/d converter preliminary user?s manual u16898ej1v0ud 161 (4) 8-bit a/d conversion result register (adcrh) this register is an 8-bit register that stores the a/d conversion result. it stores the higher 8 bits of a 10-bit resolution result. adcrh can be read by an 8-bit memory manipulation instruction. reset input makes adcrh undefined. figure 10-8. format of 8-bit a/d c onversion result register (adcrh) symbol adcrh 76543210 address: ff1ah after reset: undefined r (5) port mode control register 2 (p mc2) and port mode register 2 (pm2) when using the p20/ani0 to p23/ani3 pins for analog in put, set pmc20 to pmc23 and pm20 to pm23 to 1. at this time, the output latches of p20 to p23 may be 0 or 1. pmc2 and pm2 are set by a 1-bit or 8- bit memory manipulation instruction. reset input clears pmc2 to 00h and sets pm2 to ffh. figure 10-9. format of port m ode control register 2 (pmc2) address: ff84h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 pmc2 0 0 0 0 pmc23 pmc22 pmc21 pmc20 pmc2n operation mode specification (n = 0 to 3) 0 port mode 1 alternate-function mode (a/d converter) figure 10-10. format of port mode register 2 (pm2) address: ff22h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm2 1 1 1 1 pm23 pm22 pm21 pm20 pm2n pmn pin i/o mode selection (n = 0 to 3) 0 output mode (output buffer on) 1 input mode (output buffer off) caution when pmc20 to pmc23 are set to 1, the p20/ani 0 to p23/ani3 pins cannot be used as port pins. www..net
chapter 10 a/d converter preliminary user?s manual u16898ej1v0ud 162 10.4 a/d converter operations 10.4.1 basic operations of a/d converter <1> select one channel for a/d conversion using the analog input channel specification register (ads). <2> set adce to 1 and wait for 1 s or longer. <3> set adcs to 1 and start the conversion operation. (<4> to <10> are operations performed by hardware.) <4> the voltage input to the selected analog input c hannel is sampled by the sample & hold circuit. <5> when sampling has been done for a certain time, the sa mple & hold circuit is placed in the hold state and the input analog voltage is held until the a/d conversion operation has ended. <6> bit 9 of the successive approximation register (sar) is set. the series resistor string voltage tap is set to (1/2) av ref by the tap selector. <7> the voltage difference between the se ries resistor string voltage tap and analog input is compared by the voltage comparator. if the analog input is greater than (1/2) av ref , the msb of sar remains set to 1. if the analog input is smaller than (1/2) av ref , the msb is reset to 0. <8> next, bit 8 of sar is automatically set to 1, and t he operation proceeds to the next comparison. the series resistor string voltage tap is selected according to the preset value of bit 9, as described below. ? bit 9 = 1: (3/4) av ref ? bit 9 = 0: (1/4) av ref the voltage tap and analog input vo ltage are compared and bit 8 of sar is manipulated as follows. ? analog input voltage voltage tap: bit 8 = 1 ? analog input voltage < voltage tap: bit 8 = 0 <9> comparison is continued in this way up to bit 0 of sar. <10> upon completion of the comparison of 10 bits, an effective digital result value remains in sar, and the result value is transferred to the a/d conversion resu lt register (adcr, adcrh) and then latched. at the same time, the a/d conversion end in terrupt request (intad) can also be generated. <11> repeat steps <4> to <10>, until adcs is cleared to 0. to stop the a/d converter, clear adcs to 0. to restart a/d conversion from the st atus of adce = 1, start from <3>. to restart a/d conversion from the status of adce = 0, however, start from <2>. remark the following two types of a/d conv ersion result registers can be used. <1> adcr (16 bits): stores a 10-bit a/d conversion value. <2> adcrh (8 bits): stores an 8-bit a/d conversion value. www..net
chapter 10 a/d converter preliminary user?s manual u16898ej1v0ud 163 figure 10-11. basic operation of a/d converter conversion time sampling time sampling a/d conversion undefined conversion result a/d converter operation sar adcr, adcrh intad conversion result a/d conversion operations are performed continuously until bit 7 (adcs) of the a/d converter mode register (adm) is reset (0) by software. if a write operation is performed to adm or the analog in put channel specification r egister (ads) during an a/d conversion operation, the conversion oper ation is initialized, and if the adcs bi t is set (1), conversion starts again from the beginning. reset input makes the a/d conversion resu lt register (adcr, adcrh) undefined. www..net
chapter 10 a/d converter preliminary user?s manual u16898ej1v0ud 164 10.4.2 input voltage and conversion results the relationship between the analog input voltage input to the analog input pins (ani0 to ani3) and the theoretical a/d conversion result (stored in the 10-bit a/d conver sion result register (adcr)) is shown by the following expression. sar = int ( 1024 + 0.5) adcr = sar 64 or (adcr ? 0.5) v ain < (adcr + 0.5) where, int( ): function which returns integer part of value in parentheses v ain : analog input voltage av ref : av ref pin voltage adcr: 10-bit a/d conversion result register (adcr) value sar: successive approximation register figure 10-12 shows the relationship between the analo g input voltage and the a/d conversion result. figure 10-12. relationship between analog i nput voltage and a/d conversion result 1023 1022 1021 3 2 1 0 ffc0h ff80h ff40h 00c0h 0080h 0040h 0000h a/d conversion result (adcr) sar adcr 1 2048 1 1024 3 2048 2 1024 5 2048 input voltage/av ref 3 1024 2043 2048 1022 1024 2045 2048 1023 1024 2047 2048 1 v ain av ref av ref 1024 av ref 1024 www..net
chapter 10 a/d converter preliminary user?s manual u16898ej1v0ud 165 10.4.3 a/d converter operation mode the operation mode of the a/d converter is the select mode. one channel of analog input is selected from ani0 to ani3 by the analog input channel specification register (ads) and a/d co nversion is executed. (1) a/d conversion operation by setting bit 7 (adcs) of the a/d converter mode regist er (adm) to 1, the a/d conversion operation of the voltage, which is applied to the analog input pin specif ied by the analog input channel specification register (ads), is started. when a/d conversion has been completed, the result of the a/d c onversion is stored in t he a/d conversion result register (adcr, adcrh), and an interrupt request signal (intad) is generated. on ce the a/d conversion has started and when one a/d conversion has been comple ted, the next a/d conversion operation is immediately started. the a/d conversion operations are repeated until new data is written to ads. if adm or ads is written during a/d conversion, the a/d conversion operation under execution is stopped and restarted from the beginning. if 0 is written to adcs during a/d conversion, a/d conv ersion is immediately stopped. at this time, the conversion result is undefined. figure 10-13. a/d conversion operation anin rewriting adm adcs = 1 rewriting ads adcs = 0 anin anin anin anim anin anim anim stopped a/d conversion adcr, adcrh intad conversion is stopped conversion result is not retained remarks 1. n = 0 to 3 2. m = 0 to 3 www..net
chapter 10 a/d converter preliminary user?s manual u16898ej1v0ud 166 the setting method is described below. <1> set bit 0 (adce) of the a/d converter mode register (adm) to 1. <2> select the channel and conversion time using bi ts 1 and 0 (ads1, ads0) of the analog input channel specification register (ads) and bits 5 to 3 (fr2 to fr0) of adm. <3> set bit 7 (adcs) of adm to 1. <4> an interrupt request signal (intad) is generated. <5> transfer the a/d conversion data to the a/d conversion result register (adcr, adcrh). <6> change the channel using bits 1 and 0 (ads1, ads0) of ads. <7> an interrupt request signal (intad) is generated. <8> transfer the a/d conversion data to the a/d conversion result register (adcr, adcrh). <9> clear adcs to 0. <10> clear adce to 0. cautions 1. make sure the period of <1> to <3> is 1 s or more. 2. it is no problem if the or der of <1> and <2> is reversed. 3. <1> can be omitted. however, do not use the first conversion result after <3> in this case. 4. the period from <4> to <7> differs from the conversion time set using bits 5 to 3 (fr2 to fr0) of adm. the period from <6> to <7> is the conversion time set using fr2 to fr0. www..net
chapter 10 a/d converter preliminary user?s manual u16898ej1v0ud 167 10.5 how to read a/d converter characteristics table here, special terms unique to the a/d converter are explained. (1) resolution this is the minimum analog input vo ltage that can be identif ied. that is, the perce ntage of the analog input voltage per bit of digital output is called 1lsb (least si gnificant bit). the percentage of 1lsb with respect to the full scale is expressed by %fsr (full scale range). 1lsb is as follows when the resolution is 10 bits. 1lsb = 1/2 10 = 1/1024 = 0.098%fsr accuracy has no relation to resolution, but is determined by overall error. (2) overall error this shows the maximum error value between the actual measured value and the theoretical value. zero-scale error, full-scale error, integral linearity error, and differential linearity errors that are combinations of these express the overall error. note that the quantization error is not included in the overall erro r in the characteristics table. (3) quantization error when analog values are converted to digital values, a 1/2lsb error naturally occurs. in an a/d converter, an analog input voltage in a range of 1/2lsb is converted to the same digita l code, so a quantization error cannot be avoided. note that the quantization erro r is not included in the overall error, zero -scale error, full-scale error, integral linearity error, and differential linearity error in the characteristics table. figure 10-14. overall error figur e 10-15. quanti zation error ideal line 0 ?? 0 1 ?? 1 digital output overall error analog input av ref 0 0 ?? 0 1 ?? 1 digital output quantization error 1/2lsb 1/2lsb analog input 0 av ref (4) zero-scale error this shows the difference between the actual measuremen t value of the analog input vo ltage and the theoretical value (1/2lsb) when the digital output changes from 0......000 to 0......001. if the actual measurement value is greater than the theore tical value, it shows the difference between the actual measurement value of the analog in put voltage and the theoretical val ue (3/2lsb) when the digital output changes from 0??001 to 0??010. www..net
chapter 10 a/d converter preliminary user?s manual u16898ej1v0ud 168 (5) full-scale error this shows the difference between the actual measuremen t value of the analog input vo ltage and the theoretical value (full-scale ? 3/2lsb) when the digital output chan ges from 1......110 to 1......111. (6) integral linearity error this shows the degree to which the conversion charac teristics deviate from the ideal linear relationship. it expresses the maximum value of the difference between the actual measurement value and the ideal straight line when the zero-scale error and full-scale error are 0. (7) differential linearity error while the ideal width of code output is 1lsb, this indi cates the difference between the actual measurement value and the ideal value. figure 10-16. zero-scale error figure 10-17. full-scale error 111 011 010 001 zero-scale error ideal line 000 01 2 3 av ref digital output (lower 3 bits) analog input (lsb) 111 110 101 000 0 av ref ? 3 full-scale error ideal line analog input (lsb) digital output (lower 3 bits) av ref ? 2av ref ? 1 av ref figure 10-18. integral linearity error figure 10-19. differential linearity error 0 av ref digital output analog input integral linearity error ideal line 1 ?? 1 0 ?? 0 0 av ref digital output analog input differential linearity error 1 ?? 1 0 ?? 0 ideal 1lsb width (8) conversion time this expresses the time from the start of samp ling to when the digital output is obtained. the sampling time is included in the conv ersion time in the characteristics table. (9) sampling time this is the time the analog switch is turned on for the anal og voltage to be sampled by the sample & hold circuit. sampling time conversion time www..net
chapter 10 a/d converter preliminary user?s manual u16898ej1v0ud 169 10.6 cautions for a/d converter (1) operating current in standby mode the a/d converter stops operating in the standby mode. at this time, th e operating current can be reduced by clearing bit 7 (adcs) of the a/d conver ter mode register (adm) to 0 (see figure 10-3 ). (2) input range of ani0 to ani3 observe the rated range of the ani0 to ani3 input voltage. if a voltage of av ref or higher and v ss or lower (even in the range of absolute maximum ratings) is input to an a nalog input channel, the conver ted value of that channel becomes undefined. in addition, the converted values of the other channels may also be affected. (3) conflicting operations <1> conflict between a/d conversion result regist er (adcr, adcrh) write and adcr, adcrh read by instruction upon the end of conversion adcr, adcrh read has priority. after the read operat ion, the new conversion result is written to adcr, adcrh. <2> conflict between adcr, adcrh write and a/d converte r mode register (adm) write or analog input channel specification register (ads ) write upon the end of conversion adm or ads write has priority. adcr, adcrh write is not performed, nor is the conversion end interrupt signal (intad) generated. (4) noise countermeasures to maintain the 10-bit resolution, attention must be paid to noise input to the av ref pin and pins ani0 to ani3. because the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally, as shown in figure 10-20, to reduce noise. figure 10-20. analog input pin connection reference voltage input c = 100 to 1,000 pf if there is a possibility that noise equal to or higher than av ref or equal to or lower than v ss may enter, clamp with a diode with a small v f value (0.3 v or lower). av ref v ss ani0 to ani3 www..net
chapter 10 a/d converter preliminary user?s manual u16898ej1v0ud 170 (5) ani0/p20 to ani3/p23 <1> the analog input pins (ani0 to ani3) are also used as input port pins (p20 to p23). when a/d conversion is performed with any of an i0 to ani3 selected, do not access port 2 while conversion is in progress; otherwise th e conversion resolution may be degraded. <2> if a digital pulse is applied to the pins adjacent to th e pins currently used for a/d conversion, the expected value of the a/d conversion may not be obtained due to coupling noise. t herefore, do not apply a pulse to the pins adjacent to the pi n undergoing a/d conversion. (6) input impedance of ani0 to ani3 pins in this a/d converter, the internal sampling capacitor is charged and sampling is performed for approx. one sixth of the conversion time. since only the leakage current flows other than during sa mpling and the current for charging the capacitor also flows during sampling, the input impedance fluctuates and has no meaning. to perform sufficient sampling, howeve r, it is recommended to make the output impedance of the analog input source 10 k ? or lower, or attach a capacitor of around 100 pf to the ani0 to ani3 pins (see figure 10-20 ). (7) av ref pin input impedance a series resistor string of several tens of 10 k ? is connected between the av ref and v ss pins. therefore, if the output impedance of t he reference voltage source is high, this will result in a series connection to the series resistor string between the av ref and v ss pins, resulting in a large reference voltage error. www..net
chapter 10 a/d converter preliminary user?s manual u16898ej1v0ud 171 (8) interrupt request flag (adif) the interrupt request flag (adif) is not cleared even if th e analog input channel specification register (ads) is changed. therefore, if an analog input pin is changed during a/d conversion, the a/d conversion result and adif for the pre-change analog input may be set just before the ads rewrit e. caution is therefore re quired since, at this time, when adif is read immediately after the ads rewrite, ad if is set despite the fact a/d conversion for the post- change analog input has not ended. when a/d conversion is stopped and then resumed, clear ad if before the a/d conversion operation is resumed. figure 10-21. timing of a/d conver sion end interrupt request generation ads rewrite (start of anin conversion) a/d conversion adcr, adcrh adif anin anin anim anim anin anin anim anim ads rewrite (start of anim conversion) adif is set but anim conversion has not ended. remarks 1. n = 0 to 3 2. m = 0 to 3 (9) conversion results just after a/d conversion start the first a/d conversion value immediately after a/d conv ersion starts may not fall wit hin the rating range if the adcs bit is set to 1 within 1 s after the adce bit was set to 1, or if t he adcs bit is set to 1 with the adce bit = 0. take measures such as polling the a/d conversion end interrupt request (intad) and removing the first conversion result. (10) a/d conversion result regist er (adcr, adcrh) read operation when a write operation is performed to the a/d conver ter mode register (adm) and analog input channel specification register (ads), the contents of adcr and adcrh may become undefined. read the conversion result following conversion completion before writing to adm and ads. using a timing other than the above may cause an incorrect conversion result to be read. www..net
chapter 10 a/d converter preliminary user?s manual u16898ej1v0ud 172 (11) internal equivalent circuit the equivalent circuit of the analog input block is shown below. figure 10-22. internal equi valent circuit of anin pin anin c out c in r in lsi internal table 10-4. resistance and capaci tance values of eq uivalent circuit av ref r in c out c in 2.7 v t.b.d. t.b.d. t.b.d. 4.5 v t.b.d. t.b.d. t.b.d. remarks 1. the resistance and capacitance values shown in table 10-4 are not guaranteed values. 2. n = 0 to 3 r in : input equivalent resistance c in : input equivalent capacitance c out : package pin capacitance www..net
preliminary user?s manual u16898ej1v0ud 173 chapter 11 serial interface uart6 11.1 functions of serial interface uart6 serial interface uart6 has the following two modes. (1) operation stop mode this mode is used when serial communication is not executed and can enable a reduction in the power consumption. for details, see 11.4.1 operation stop mode . (2) asynchronous serial interface (uart) mode this mode supports the lin (local interconnect network) -bus. the functions of this mode are outlined below. for details, see 11.4.2 asynchronous seri al interface (uart) mode and 11.4.3 dedicated baud rate generator . ? two-pin configuration t x d6: transmit data output pin r x b6: receive data input pin ? data length of communication data can be selected from 7 or 8 bits. ? dedicated internal 8-bit baud rate generator allowing any baud rate to be set ? transmission and reception can be performed independently. ? twelve operating clock inputs selectable ? msb- or lsb-first communication selectable ? inverted transmission operation ? synchronous break field transmission from 13 to 20 bits ? more than 11 bits can be identified for synchronous break field reception (sbf reception flag provided). cautions 1. the t x d6 output inversion function inverts only th e transmission side and not the reception side. to use this f unction, the reception side must be ready for reception of inverted data. 2. if clock supply to serial interface uart6 is not stopped (e .g., in the halt mode), normal operation continues. if clock supply to serial interface uart6 is stopped (e.g., in the stop mode), each register stops ope rating, and holds the value i mmediately before clock supply was stopped. the t x d6 pin also holds the value imme diately before clock supply was stopped and outputs it. how ever, the operation is not guara nteed after clock supply is resumed. therefore, reset the circuit so th at power6 = 0, rxe6 = 0, and txe6 = 0. 3. if data is continuously transmitted, the communication timi ng from the stop bit to the next start bit is extended two operating clocks of the macro. however, th is does not affect the result of communication because the recepti on side initializes the timing when it has detected a start bit. do not use the contin uous transmission function if the interface is incorporated in lin. www..net
chapter 11 serial interface uart6 preliminary user?s manual u16898ej1v0ud 174 remark lin stands for local interconnect network and is a low-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automotive network. lin communication is single-master communication, and up to 15 slaves can be connected to one master. the lin slaves are used to contro l the switches, actuator s, and sensors, and thes e are connected to the lin master via the lin network. normally, the lin master is connected to a network such as can (controller area network). in addition, the lin bus uses a single-wire method and is connected to the nodes via a transceiver that complies with iso9141. in the lin protocol, the master transmits a frame with baud rate information and the slave receives it and corrects the baud rate error. therefore, communication is possible when the baud rate error in the slave is 15% or less. figures 11-1 and 11-2 outline the transmissi on and reception operations of lin. figure 11-1. lin transmission operation sleep bus wakeup signal frame 8 bits note 1 55h transmission data transmission data transmission data transmission data transmission 13-bit note 2 sbf transmission note 3 synchronous break field synchronous field indent field data field data field checksum field tx6 intst6 notes 1. the wakeup signal frame is substituted by 80h transmission in the 8-bit mode. 2. the synchronous break field is output by hardware. the output width is equal to the bit length set by bits 4 to 2 (sbl62 to sbl60) of asynchronous serial interface control register 6 (asicl6). if the output width needs to be adjusted more accurately, use baud rate generator control register 6 (brgc6) (see 11.4.2 (h) sbf transmission ). 3. intst6 is output on completion of each transmissi on. it is also output when sbf is transmitted. remark the interval between each field is controlled by software. www..net
chapter 11 serial interface uart6 preliminary user?s manual u16898ej1v0ud 175 figure 11-2. lin reception operation sleep bus 13 bits note 2 sf reception id reception data reception data reception data reception note 5 note 3 note 1 note 4 wakeup signal frame synchronous break field synchronous field indent field data field data field checksum field rx6 sbf reception reception interrupt (intsr6) edge detection (intp0) capture timer disable enable disable enable notes 1. the wakeup signal is detected at the edge of the pin, and enables uart6 and sets the sbf reception mode. 2. reception continues until the stop bit is detected. when an sbf wit h low-level data of 11 bits or more has been detected, it is assumed that sbf reception has been completed correctly, and an interrupt signal is output. if an sbf with low-level da ta of less than 11 bits has been detected, it is assumed that an sbf reception error has occurred. the interrupt signal is not output and the sbf reception mode is restored. 3. if sbf reception has been completed correctly, an interrupt signal is output. this sbf reception completion interrupt enables the capture timer. detection of errors ove6, pe6, and fe6 is suppressed, and error detection processing of ua rt communication and data transfer of the shift register and rxb6 is not performed. the shift register holds the reset value ffh. 4. calculate the baud rate error from the bit length of the synchronous field, disable uart6 after sf reception, and then re-set baud rate gen erator control register 6 (brgc6). 5. distinguish the checksum field by software. also perform processi ng by software to initialize uart6 after reception of the checksum field an d to set the sbf reception mode again. to perform a lin receive operation, use a conf iguration like the one shown in figure 11-3. the wakeup signal transmitted from the lin master is re ceived by detecting the edge of the external interrupt (intp0). the length of the synchronous field transmitted from the lin master can be measured using the external event capture operation of 16-bit ti mer/event counter 00, and the bau d rate error can be calculated. the input signal of the reception port input (rxd6) ca n be input to the external interrupt (intp0) and 16-bit timer/event counter 00 by port input switch control (isc0/isc1), without co nnecting rxd6 and intp0/ti000 externally. www..net
chapter 11 serial interface uart6 preliminary user?s manual u16898ej1v0ud 176 figure 11-3. port configurati on for lin reception operation rxd6 input intp0 input ti000 input p44/r x d6 p30/intp0/ti000 port input selection control (isc0) 0: selects intp0 (p30). 1: selects rxd6 (p44). selector port mode (pm44) output latch (p44) port mode (pm30) output latch (p30) port input selection control (isc1) 0: selects ti000 (p30). 1: selects rxd6 (p44). selector selector selector remark isc0, isc1: bits 0 and 1 of the input switch control register (isc) (see figure 11-11 ) the peripheral functions used in the lin communication operation are shown below. ? external interrupt (intp0); wakeup signal detection use: detects the wakeup signal edges and detects start of communication. ? 16-bit timer/event counter 00 (ti000); baud rate error detection use: detects the baud rate error (m easures the ti000 input edge interval in the capture mode) by detecting the synchronous break field (sbf) length and divides it by the number of bits. ? serial interface uart6 www..net
chapter 11 serial interface uart6 preliminary user?s manual u16898ej1v0ud 177 11.2 configuration of serial interface uart6 serial interface uart6 consis ts of the following hardware. table 11-1. configurati on of serial interface uart6 item configuration registers receive buffer register 6 (rxb6) receive shift register 6 (rxs6) transmit buffer register 6 (txb6) transmit shift register 6 (txs6) control registers asynchronous serial interface o peration mode register 6 (asim6) asynchronous serial interface recepti on error status register 6 (asis6) asynchronous serial interface transm ission status register 6 (asif6) clock selection register 6 (cksr6) baud rate generator control register 6 (brgc6) asynchronous serial interface control register 6 (asicl6) input switch control register (isc) port mode register 4 (pm4) port register 4 (p4) www..net
chapter 11 serial interface uart6 preliminary user?s manual u16898ej1v0ud 178 figure 11-4. block diagram of serial interface uart6 internal bus asynchronous serial interface control register 6 (asicl6) transmit buffer register 6 (txb6) transmit shift register 6 (txs6) t x d6/ intp1/p43 intst6 baud rate generator asynchronous serial interface control register 6 (asicl6) reception control receive shift register 6 (rxs6) receive buffer register 6 (rxb6) r x d6/ p44 ti000, intp0 note intsr6 baud rate generator filter intsre6 asynchronous serial interface reception error status register 6 (asis6) asynchronous serial interface operation mode register 6 (asim6) asynchronous serial interface transmission status register 6 (asif6) transmission control registers f xp f xp /2 f xp /2 2 f xp /2 3 f xp /2 4 f xp /2 5 f xp /2 6 f xp /2 7 f xp /2 8 f xp /2 9 f xp /2 10 f xp /2 11 8 reception unit transmission unit clock selection register 6 (cksr6) baud rate generator control register 6 (brgc6) output latch (p43) pm43 8 selector note selectable with input switch control register (isc). www..net
chapter 11 serial interface uart6 preliminary user?s manual u16898ej1v0ud 179 (1) receive buffer register 6 (rxb6) this 8-bit register stores parallel data conv erted by receive shift register 6 (rxs6). each time 1 byte of data has been received, new receive data is transferred to this register from receive shift register 6 (rxs6). if the data length is set to 7 bits, data is transferred as follows. ? in lsb-first reception, the receive data is transferred to bits 0 to 6 of rxb6 and the msb of rxb6 is always 0. ? in msb-first reception, the receive data is transferred to bits 1 to 7 of rxb6 and the lsb of rxb6 is always 0. if an overrun error (ove6) occurs, the rece ive data is not transferred to rxb6. rxb6 can be read by an 8-bit memory manipulation inst ruction. no data can be written to this register. reset input sets this register to ffh. (2) receive shift register 6 (rxs6) this register converts the serial data input to the r x d6 pin into parallel data. rxs6 cannot be directly manipulated by a program. (3) transmit buffer register 6 (txb6) this buffer register is used to set transmit data. tr ansmission is started when data is written to txb6. this register can be read or written by an 8-bit memory manipulation instruction. reset input sets this register to ffh. cautions 1. do not write data to txb6 when bi t 1 (txbf6) of asynchronous serial interface transmission status register 6 (asif6) is 1. 2. do not refresh (write the same value to) txb6 by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asynchr onous serial interface operation mode register 6 (asim6) are 1 or when bit 7 (power6) and bit 5 (rxe6) of asim6 are 1). (4) transmit shift register 6 (txs6) this register transmits the data transferred from txb6 from the t x d6 pin as serial data. data is transferred from txb6 immediately after txb6 is written for the first tr ansmission, or immediately before intst6 occurs after one frame was transmitted for continuous transmission. da ta is transferred from txb6 and transmitted from the t x d6 pin at the falling edge of the base clock. txs6 cannot be directly manipulated by a program. www..net
chapter 11 serial interface uart6 preliminary user?s manual u16898ej1v0ud 180 11.3 registers controlling serial interface uart6 serial interface uart6 is controlle d by the following nine registers. ? asynchronous serial interface operation mode register 6 (asim6) ? asynchronous serial interface recept ion error status register 6 (asis6) ? asynchronous serial interface transmission status register 6 (asif6) ? clock selection register 6 (cksr6) ? baud rate generator control register 6 (brgc6) ? asynchronous serial interface control register 6 (asicl6) ? input switch control register (isc) ? port mode register 4 (pm4) ? port register 4 (p4) (1) asynchronous serial interface ope ration mode register 6 (asim6) this 8-bit register controls the serial comm unication operations of serial interface uart6. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 01h. remark asim6 can be refreshed (the same value is wr itten) by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asim6 = 1 or bit 7 (power6) and bit 5 (rxe6) of asim6 = 1). figure 11-5. format of asynchronous serial inte rface operation mode register 6 (asim6) (1/2) address: ff90h after reset: 01h r/w symbol <7> <6> <5> 4 3 2 1 0 asim6 power6 txe6 rxe6 ps61 ps60 cl6 sl6 isrm6 power6 enabling/disabling operat ion of internal operation clock 0 note 1 disable operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit note 2 . 1 note 3 enable operation of the internal operation clock txe6 enabling/disabling transmission 0 disable transmission (synchronously reset the transmission circuit). 1 enable transmission notes 1. the output of the t x d6 pin goes high and the input from the r x d6 pin is fixed to the high level when power6 = 0. 2. asynchronous serial interface reception error status register 6 (asis6), asynchronous serial interface transmission status register 6 (asif6), bit 7 ( sbrf6) and bit 6 (sbrt6) of asynchronous serial interface control register 6 (asicl6), and receive buffer register 6 (rxb6) are reset. 3. operation of the 8-bit counter out put is enabled at the second base clock after 1 is written to the power6 bit. www..net
chapter 11 serial interface uart6 preliminary user?s manual u16898ej1v0ud 181 figure 11-5. format of asynchronous serial inte rface operation mode register 6 (asim6) (2/2) rxe6 enabling/disabling reception 0 disable reception (synchronous ly reset the reception circuit). 1 enable reception ps61 ps60 transmission oper ation reception operation 0 0 parity bit not output. reception without parity 0 1 output 0 parity. reception as 0 parity note 1 0 output odd parity. judge as odd parity. 1 1 output even parity. judge as even parity. cl6 specification of character length of transmit/receive data 0 character length of data = 7 bits 1 character length of data = 8 bits sl6 specification of number of stop bits of transmit data 0 number of stop bits = 1 1 number of stop bits = 2 isrm6 enabling/disabling occurrence of recept ion completion interrupt in case of error 0 ?intsre6? occurs in case of error (at this time, intsr6 does not occur). 1 ?intsr6? occurs in case of error (at this time, intsre6 does not occur). note if ?reception as 0 parity? is selected, the parity is not judged. therefore, bit 2 (pe6) of asynchronous serial interface reception error status register 6 (asis6) is not set and the error interrupt does not occur. cautions 1. at startup, set power6 to 1 and then set txe6 to 1. to stop the op eration, clear txe6 to 0, and then clear power6 to 0. 2. at startup, set power6 to 1 and then set rxe6 to 1. to stop the operation, clear rxe6 to 0, and then clear power6 to 0. 3. set power6 to 1 and then set rxe6 to 1 wh ile a high level is input to the rxd6 pin. if power6 is set to 1 and rxe6 is set to 1 wh ile a low level is input, reception is started. 4. clear the txe6 and rxe6 bits to 0 be fore rewriting the ps61, ps60, and cl6 bits. 5. fix the ps61 and ps60 bits to 0 when mounting the device on lin. 6. make sure that txe6 = 0 wh en rewriting the sl6 bit. recep tion is always performed with ?the number of stop bits = 1?, and therefore, is not affected by the set value of the sl6 bit. 7. make sure that rxe6 = 0 when rewriting the isrm6 bit. www..net
chapter 11 serial interface uart6 preliminary user?s manual u16898ej1v0ud 182 (2) asynchronous serial interface recepti on error status register 6 (asis6) this register indicates an error status on completion of reception by serial interface uart6. it includes three error flag bits (pe6, fe6, ove6). this register is read-only by an 8-bit memory manipulation instruction. reset input clears this register to 00h if bit 7 (power6) and bit 5 (rxe6) of asim6 = 0. 00h is read when this register is read. figure 11-6. format of asynchronous serial inte rface reception error status register 6 (asis6) address: ff93h after reset: 00h r symbol 7 6 5 4 3 2 1 0 asis6 0 0 0 0 0 pe6 fe6 ove6 pe6 status flag indicating parity error 0 if power6 = 0 and rxe6 = 0, or if asis6 register is read 1 if the parity of transmit data does not match the parity bit on completion of reception fe6 status flag indicating framing error 0 if power6 = 0 and rxe6 = 0, or if asis6 register is read 1 if the stop bit is not detected on completion of reception ove6 status flag indicating overrun error 0 if power6 = 0 and rxe6 = 0, or if asis6 register is read 1 if receive data is set to the rxb register and the next reception operation is completed before the data is read. cautions 1. the operation of the pe6 bit differs depending on the set values of the ps61 and ps60 bits of asynchronous serial interface operati on mode register 6 (asim6). 2. the first bit of the receive data is checked as the stop bit, regardless of the number of stop bits. 3. if an overrun error occurs, the next receive data is not wri tten to receive buffer register 6 (rxb6) but discarded. www..net
chapter 11 serial interface uart6 preliminary user?s manual u16898ej1v0ud 183 (3) asynchronous serial interface tran smission status register 6 (asif6) this register indicates the status of transmission by se rial interface uart6. it includes two status flag bits (txbf6 and txsf6). transmission can be continued without disruption even during an interrupt period, by writing the next data to the txb6 register after data has been transferred from the txb6 register to the txs6 register. this register is read-only by an 8-bit memory manipulation instruction. reset input clears this register to 00h if bit 7 (power6) and bit 6 (txe6) of asim6 = 0. figure 11-7. format of asynchronous serial in terface transmission status register 6 (asif6) address: ff95h after reset: 00h r symbol 7 6 5 4 3 2 1 0 asif6 0 0 0 0 0 0 txbf6 txsf6 txbf6 transmit buffer data flag 0 if power6 = 0 or txe6 = 0, or if data is tr ansferred to transmit shift register 6 (txs6) 1 if data is written to transmit buffer register 6 (txb6) (if data exists in txb6) txsf6 transmit shift register data flag 0 if power6 = 0 or txe6 = 0, or if the next data is not transferred from transmit buffer register 6 (txb6) after completion of transfer 1 if data is transferred from transmit buffer regist er 6 (txb6) (if data transmi ssion is in progress) cautions 1. to transmit data conti nuously, write the first transmit data (first byte) to the txb6 register. be sure to check that the txbf6 fl ag is ?0?. if so, write the next transmit data (second byte) to the txb6 register. if data is written to th e txb6 register while the txbf6 flag is ?1?, the transmit data cannot be guaranteed. 2. to initialize the transmission unit upon comple tion of continuous transmission, be sure to check that the txsf6 flag is ?0? after genera tion of the transmission completion interrupt, and then execute initialization. if initializati on is executed while the txsf6 flag is ?1?, the transmit data cannot be guaranteed. www..net
chapter 11 serial interface uart6 preliminary user?s manual u16898ej1v0ud 184 (4) clock selection register 6 (cksr6) this register selects the base cl ock of serial interface uart6. cksr6 can be set by an 8-bit memory manipulation instruction. reset input clears this register to 00h. remark cksr6 can be refreshed (the same value is writ ten) by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asim6 = 1 or bit 7 (power6) and bit 5 (rxe6) of asim6 = 1). figure 11-8. format of clock selection register 6 (cksr6) address: ff96h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 cksr6 0 0 0 0 tps63 tps62 tps61 tps60 tps63 tps62 tps61 tps60 base clock (f xclk6 ) selection 0 0 0 0 f xp (10 mhz) 0 0 0 1 f xp /2 (5 mhz) 0 0 1 0 f xp /2 2 (2.5 mhz) 0 0 1 1 f xp /2 3 (1.25 mhz) 0 1 0 0 f xp /2 4 (625 khz) 0 1 0 1 f xp /2 5 (312.5 khz) 0 1 1 0 f xp /2 6 (156.25 khz) 0 1 1 1 f xp /2 7 (78.13 khz) 1 0 0 0 f xp /2 8 (39.06 khz) 1 0 0 1 f xp /2 9 (19.53 khz) 1 0 1 0 f xp /2 10 (9.77 khz) 1 0 1 1 f xp /2 11 (4.89 khz) other than above setting prohibited caution make sure power6 = 0 wh en rewriting tps63 to tps60. remarks 1. figures in parentheses are for operation with f xp = 10 mhz 2. f xp : oscillation frequency of clock to peripheral hardware www..net
chapter 11 serial interface uart6 preliminary user?s manual u16898ej1v0ud 185 (5) baud rate generator c ontrol register 6 (brgc6) this register sets the division value of t he 8-bit counter of serial interface uart6. brgc6 can be set by an 8-bit memory manipulation instruction. reset input sets this register to ffh. remark brgc6 can be refreshed (the same value is wr itten) by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asim6 = 1 or bit 7 (power6) and bit 5 (rxe6) of asim6 = 1). figure 11-9. format of baud rate ge nerator control register 6 (brgc6) address: ff97h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 brgc6 mdl67 mdl66 mdl65 mdl64 mdl63 mdl62 mdl61 mdl60 mdl67 mdl66 mdl65 mdl64 mdl63 mdl62 mdl61 mdl60 k output clock selection of 8-bit counter 0 0 0 0 0 setting prohibited 0 0 0 0 1 0 0 0 8 f xclk6 /8 0 0 0 0 1 0 0 1 9 f xclk6 /9 0 0 0 0 1 0 1 0 10 f xclk6 /10 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 1 1 1 1 1 0 0 252 f xclk6 /252 1 1 1 1 1 1 0 1 253 f xclk6 /253 1 1 1 1 1 1 1 0 254 f xclk6 /254 1 1 1 1 1 1 1 1 255 f xclk6 /255 cautions 1. make sure that bit 6 (txe6) and bit 5 (r xe6) of the asim6 register = 0 when rewriting the mdl67 to mdl60 bits. 2. the baud rate is the output clo ck of the 8-bit counter divided by 2. remarks 1. f xclk6 : frequency of base clock selected by the t ps63 to tps60 bits of cksr6 register 2. k: value set by mdl67 to mdl60 bits (k = 8, 9, 10, ..., 255) 3. : don?t care www..net
chapter 11 serial interface uart6 preliminary user?s manual u16898ej1v0ud 186 (6) asynchronous serial interface control register 6 (asicl6) this register controls the serial communicati on operations of serial interface uart6. asicl6 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 16h. caution asicl6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (power6) and bit 6 (txe6) of asim6 = 1 or bit 7 (power6) and bit 5 (rxe6) of asim6 = 1). note, however, that comm unication is started by the refresh operation because bit 6 (sbrt6) of asicl6 is cleared to 0 when communication is completed (when an interrupt signal is generated). figure 11-10. format of asynchronous serial interface control register 6 (asicl6) (1/2) address: ff98h after reset: 16h r/w note symbol <7> <6> 5 4 3 2 1 0 asicl6 sbrf6 sbrt6 sbtt6 sbl62 sbl61 sbl60 dir6 txdlv6 sbrf6 sbf reception status flag 0 if power6 = 0 and rxe6 = 0 or if sbf reception has been completed correctly 1 sbf reception in progress sbrt6 sbf reception trigger 0 ? 1 sbf reception trigger sbtt6 sbf transmission trigger 0 ? 1 sbf transmission trigger note bit 7 is read-only. www..net
chapter 11 serial interface uart6 preliminary user?s manual u16898ej1v0ud 187 figure 11-10. format of asynchronous serial interface control register 6 (asicl6) (2/2) sbl62 sbl61 sbl60 sbf transmission output width control 1 0 1 sbf is output with 13-bit length. 1 1 0 sbf is output with 14-bit length. 1 1 1 sbf is output with 15-bit length. 0 0 0 sbf is output with 16-bit length. 0 0 1 sbf is output with 17-bit length. 0 1 0 sbf is output with 18-bit length. 0 1 1 sbf is output with 19-bit length. 1 0 0 sbf is output with 20-bit length. dir6 specification of first bit 0 msb 1 lsb txdlv6 enabling/disabling inverting t x d6 output 0 normal output of t x d6 1 inverted output of t x d6 cautions 1. in the case of an sbf reception error, return the mode to the sb f reception mode and hold the status of the sbrf6 flag. 2. before setting the sbrt6 bi t, make sure that bit 7 (power6) and bit 5 (rxe6) of asim6 = 1. 3. the read value of the sbrt6 bit is always 0. sbrt6 is automatically cleared to 0 after sbf reception has been co rrectly completed. 4. before setting the sbtt6 bit to 1, make sure that bit 7 (pow er6) and bit 6 (txe6) of asim6 = 1. 5. the read value of the sbtt6 bit is always 0. sbtt6 is automatically cleared to 0 at the end of sbf transmission. 6. before rewriting the dir6 and txdlv6 bits, clear the txe6 a nd rxe6 bits to 0. www..net
chapter 11 serial interface uart6 preliminary user?s manual u16898ej1v0ud 188 (7) input switch control register (isc) the input switch control register (isc) is used to receiv e a status signal transmitted from the master during lin (local interconnect network) reception. the input signal is switched by setting isc. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 11-11. format of input s witch control register (isc) address: ff8ch after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 isc 0 0 0 0 0 0 isc1 isc0 isc1 ti000 input source selection 0 ti000 (p30) 1 rxd6 (p44) isc0 intp0 input source selection 0 intp0 (p30) 1 rxd6 (p44) (8) port mode register 4 (pm4) this register sets port 4 input/output in 1-bit units. when using the p43/txd6/intp1 pin for serial interface da ta output, clear pm43 to 0 and set the output latch of p43 to 1. when using the p44/rxd6 pin for serial interface data input, set pm44 to 1. the output latch of p44 at this time may be 0 or 1. pm4 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to ffh. figure 11-12. format of port mode register 4 (pm4) address: ff24h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm4 1 1 pm45 pm44 pm43 pm42 pm41 pm40 pm4n p4n pin i/o mode selection (n = 0 to 5) 0 output mode (output buffer on) 1 input mode (output buffer off) www..net
chapter 11 serial interface uart6 preliminary user?s manual u16898ej1v0ud 189 11.4 operation of serial interface uart6 serial interface uart6 has the following two modes. ? operation stop mode ? asynchronous serial interface (uart) mode 11.4.1 operation stop mode in this mode, serial communication cannot be executed; theref ore, the power consumption can be reduced. in addition, the pins can be used as ordinary port pins in this mode. to set the operation st op mode, clear bits 7, 6, and 5 (power6, txe6, and rxe6) of asim6 to 0. (1) register used the operation stop mode is set by asynchronous serial interface operation mode register 6 (asim6). asim6 can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 01h. address: ff90h after reset: 01h r/w symbol <7> <6> <5> 4 3 2 1 0 asim6 power6 txe6 rxe6 ps61 ps60 cl6 sl6 isrm6 power6 enabling/disabling operat ion of internal operation clock 0 note 1 disable operation of the internal operation clock (fix the clock to low level) and asynchronously reset the internal circuit note 2 . txe6 enabling/disabling transmission 0 disable transmission operat ion (synchronously reset the transmission circuit). rxe6 enabling/disabling reception 0 disable reception (synchronous ly reset the reception circuit). notes 1. the output of the t x d6 pin goes high and the input from the r x d6 pin is fixed to high level when power6 = 0. 2. asynchronous serial interface reception error status register 6 (asis6), asynchronous serial interface transmission status register 6 (asif6), bit 7 ( sbrf6) and bit 6 (sbrt6) of asynchronous serial interface control register 6 (asicl6), and receive buffer register 6 (rxb6) are reset. caution clear power6 to 0 after clearing txe6 and rxe6 to 0 to set the operation stop mode. to start the operation, set power6 to 1, and then set txe6 and rxe6 to 1. remark to use the rxd6/p44 and txd6/intp1/p43 pins as general-purpose port pins, see chapter 4 port functions . www..net
chapter 11 serial interface uart6 preliminary user?s manual u16898ej1v0ud 190 11.4.2 asynchronous serial interface (uart) mode in this mode, data of 1 byte is transmitted/received following a start bit, and a full-duplex operation can be performed. a dedicated uart baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates. (1) registers used ? asynchronous serial interface operation mode register 6 (asim6) ? asynchronous serial interface recept ion error status register 6 (asis6) ? asynchronous serial interface transmission status register 6 (asif6) ? clock selection register 6 (cksr6) ? baud rate generator control register 6 (brgc6) ? asynchronous serial interface control register 6 (asicl6) ? input switch control register (isc) ? port mode register 4 (pm4) ? port register 4 (p4) the basic procedure of setting an operatio n in the uart mode is as follows. <1> set the cksr6 register (see figure 11-8 ). <2> set the brgc6 register (see figure 11-9 ). <3> set bits 0 to 4 (isrm6, sl6, cl6, ps60, ps61) of the asim6 register (see figure 11-5 ). <4> set bits 0 and 1 (txdlv6, di r6) of the asicl6 register (see figure 11-10 ). <5> set bit 7 (power6) of the asim6 register to 1. <6> set bit 6 (txe6) of the asim6 register to 1. transmission is enabled. set bit 5 (rxe6) of the asim6 register to 1. reception is enabled. <7> write data to transmit buffer register 6 (txb6). data transmission is started. caution take relationship with the other party of communication into consid eration when setting the port mode register and port register. www..net
chapter 11 serial interface uart6 preliminary user?s manual u16898ej1v0ud 191 the relationship between the register settings and pins is shown below. table 11-2. relationship between register settings and pins pin function power6 txe6 rxe6 pm43 p43 pm44 p44 uart6 operation txd6/intp1/p43 rxd6/p44 0 0 0 note note note note stop p43 p44 0 1 note note 1 reception p43 rxd6 1 0 0 1 note note transmission txd6 p44 1 1 1 0 1 1 transmission/ reception txd6 rxd6 note can be set as port function. remark : don?t care power6: bit 7 of asynchronous serial interface operation mode register 6 (asim6) txe6: bit 6 of asim6 rxe6: bit 5 of asim6 pm4: port mode register p4: port output latch www..net
chapter 11 serial interface uart6 preliminary user?s manual u16898ej1v0ud 192 (2) communication operation (a) format and waveform example of normal transmit/receive data figures 11-13 and 11-14 show the format and waveform example of the normal transmit/receive data. figure 11-13. format of normal uart transmit/receive data 1. lsb-first transmission/reception start bit parity bit d0 d1 d2 d3 d4 1 data frame character bits d5 d6 d7 stop bit 2. msb-first transmission/reception start bit parity bit d7 d6 d5 d4 d3 1 data frame character bits d2 d1 d0 stop bit one data frame consists of the following bits. ? start bit ... 1 bit ? character bits ... 7 or 8 bits ? parity bit ... even parity, odd parity, 0 parity, or no parity ? stop bit ... 1 or 2 bits the character bit length, parity, and stop bit length in one data frame are specified by asynchronous serial interface operation mode register 6 (asim6). whether data is communicated with the lsb or msb first is specified by bit 1 (dir6) of asynchronous serial interface control register 6 (asicl6). whether the t x d6 pin outputs normal or inverted data is s pecified by bit 0 (txdlv6) of asicl6. www..net
chapter 11 serial interface uart6 preliminary user?s manual u16898ej1v0ud 193 figure 11-14. example of normal uart transmit/receive data waveform 1. data length: 8 bits, lsb first, parity: even parity, stop bit: 1 bit, communication data: 55h 1 data frame start d0 d1 d2 d3 d4 d5 d6 d7 parity stop 2. data length: 8 bits, msb first, parity: even parity, stop bit: 1 bit, communication data: 55h 1 data frame start d7 d6 d5 d4 d3 d2 d1 d0 parity stop 3. data length: 8 bits, msb first, parity: even parity, stop bit: 1 bit, communication data: 55h, t x d6 pin inverted output 1 data frame start d7 d6 d5 d4 d3 d2 d1 d0 parity stop 4. data length: 7 bits, lsb first, parity: o dd parity, stop bit: 2 bits, communication data: 36h 1 data frame start d0 d1 d2 d3 d4 d5 d6 parity stop stop 5. data length: 8 bits, lsb first, parity: none, stop bit: 1 bit, communication data: 87h 1 data frame start d0 d1 d2 d3 d4 d5 d6 d7 stop www..net
chapter 11 serial interface uart6 preliminary user?s manual u16898ej1v0ud 194 (b) parity types and operation the parity bit is used to detect a bit error in communica tion data. usually, the same type of parity bit is used on both the transmission and reception sides. with even parity and odd parity, a 1-bit (odd number) error can be detected. with zero parity and no parity, an error cannot be detected. caution fix the ps61 and ps60 bits to 0 wh en the device is inco rporated in lin. (i) even parity ? transmission transmit data, including the parity bit, is controlled so that the number of bits that are ?1? is even. the value of the parity bit is as follows. if transmit data has an odd number of bits that are ?1?: 1 if transmit data has an even number of bits that are ?1?: 0 ? reception the number of bits that are ?1? in the receive dat a, including the parity bit, is counted. if it is odd, a parity error occurs. (ii) odd parity ? transmission unlike even parity, transmit data, including the parity bit, is controlled so that the number of bits that are ?1? is odd. if transmit data has an odd number of bits that are ?1?: 0 if transmit data has an even number of bits that are ?1?: 1 ? reception the number of bits that are ?1? in the receive data, including the parit y bit, is counted. if it is even, a parity error occurs. (iii) 0 parity the parity bit is cleared to 0 when data is transmitted, regardless of the transmit data. the parity bit is not detected when the data is received. therefore, a parity error does not occur regardless of whether the parity bit is ?0? or ?1?. (iv) no parity no parity bit is appended to the transmit data. reception is performed assuming that there is no par ity bit when data is received. because there is no parity bit, a parity error does not occur. www..net
chapter 11 serial interface uart6 preliminary user?s manual u16898ej1v0ud 195 (c) normal transmission the t x d6 pin outputs a high level when bit 7 (power6) of asynchronous serial interface operation mode register 6 (asim6) is set to 1. if bit 6 (txe6) of asim6 is then set to 1, transmission is enabled. transmission can be started by writing transmit data to tr ansmit buffer register 6 (txb6). the start bit, parity bit, and stop bit are automatica lly appended to the data. when transmission is started, the data in txb6 is transferred to transmit sh ift register 6 (txs6). after that, the data is sequentially out put from txs6 to the t x d6 pin. when transmission is completed, the parity and stop bits set by asim6 are appended and a transmission co mpletion interrupt reques t (intst6) is generated. transmission is stopped until the data to be transmitted next is written to txb6. figure 11-15 shows the timing of the transmission comp letion interrupt request (intst6). this interrupt occurs as soon as the last stop bit has been output. figure 11-15. normal transmission comp letion interrupt request timing 1. stop bit length: 1 intst6 d0 start d1 d2 d6 d7 stop t x d6 (output) parity 2. stop bit length: 2 t x d6 (output) intst6 d0 start d1 d2 d6 d7 parity stop www..net
chapter 11 serial interface uart6 preliminary user?s manual u16898ej1v0ud 196 (d) continuous transmission the next transmit data can be written to transmit buffer re gister 6 (txb6) as soon as transmit shift register 6 (txs6) has started its shift operation. consequently, even while the intst6 interrupt is being serviced after transmission of one data frame, data can be continuously transmitted and an efficient communication rate can be realized. in addition, the txb6 register can be e fficiently written twice (2 bytes) without having to wait for the transmission time of one data frame, by readi ng bit 0 (txsf6) of asynchronous serial interface transmission status register 6 (asif6) when the transmission completion interrupt has occurred. to transmit data continuously, be sure to reference the asif6 register to check the transmission status and whether the txb6 register can be written, and then write the data. cautions 1. the txbf6 and txsf6 flags of the asis register change from ?10? to ?11?, and to ?01? during continuous transmission. to check the status, therefore, do not use a combination of the txbf6 a nd txsf6 flags for judgment. read only the txbf6 flag when executing continuous transmission. 2. when the device is incorp orated in a lin, the continuous transmission function cannot be used. make sure that a synchronous serial interface tran smission status register 6 (asif6) is 00h before writin g transmit data to transmit buffer register 6 (txb6). txbf6 writing to txb6 register 0 writing enabled 1 writing disabled caution to transmit data continuously, write the first transmit data (fi rst byte) to the txb6 register. be sure to check that the txbf6 fl ag is ?0?. if so, write the next transmit da ta (second byte) to the txb6 register. if data is written to the txb6 register while the txbf6 flag is ?1?, the transmit data cannot be guaranteed. the communication status can be checked using the txsf6 flag. txsf6 transmission status 0 transmission is completed. 1 transmission is in progress. cautions 1. to initialize the transmission unit upon completion of continuous transmission, be sure to check that the txsf6 flag is ?0? afte r generation of the transmission completion interrupt, and then execute initialization. if initialization is executed while the txsf6 flag is ?1?, the transmit data cannot be guaranteed. 2. during continuous transmission, an ove rrun error may occur, which means that the next transmission was completed before exe cution of intst6 interrupt servicing after transmission of one data frame. an ove rrun error can be detected by developing a program that can count the number of transmit data and by refere ncing the txsf6 flag. www..net
chapter 11 serial interface uart6 preliminary user?s manual u16898ej1v0ud 197 figure 11-16 shows an example of the continuous transmission processing flow. figure 11-16. example of contin uous transmission processing flow write txb6. set registers. write txb6. transfer executed necessary number of times? yes read asif6 txbf6 = 0? no no yes transmission completion interrupt occurred? read asif6 txsf6 = 0? no no no yes yes yes yes completion of transmission processing transfer executed necessary number of times? remark txb6: transmit buffer register 6 asif6: asynchronous serial interface transmission status register 6 txbf6: bit 1 of asif6 (transmit buffer data flag) txsf6: bit 0 of asif6 (trans mit shift register data flag) www..net
chapter 11 serial interface uart6 preliminary user?s manual u16898ej1v0ud 198 figure 11-17 shows the timing of starting continuous transmission, and figure 11-18 shows the timing of ending continuous transmission. figure 11-17. timing of starting continuous transmission t x d6 start intst6 data (1) data (1) data (2) data (3) data (2) data (1) data (3) ff ff parity stop data (2) parity stop txb6 txs6 txbf6 txsf6 start start note note when asif6 is read, there is a period in which t xbf6 and txsf6 = 1, 1. therefore, judge whether writing is enabled using only the txbf6 bit. remark t x d6: t x d6 pin (output) intst6: interrupt request signal txb6: transmit buffer register 6 txs6: transmit shift register 6 asif6: asynchronous serial interface transmission status register 6 txbf6: bit 1 of asif6 txsf6: bit 0 of asif6 www..net
chapter 11 serial interface uart6 preliminary user?s manual u16898ej1v0ud 199 figure 11-18. timing of ending continuous transmission t x d6 start intst6 data (n ? 1) data (n ? 1) data (n) data (n) data (n ? 1) ff parity stop stop data (n) parity stop txb6 txs6 txbf6 txsf6 power6 or txe6 start remark t x d6: t x d6 pin (output) intst6: interrupt request signal txb6: transmit buffer register 6 txs6: transmit shift register 6 asif6: asynchronous serial interface transmission status register 6 txbf6: bit 1 of asif6 txsf6: bit 0 of asif6 power6: bit 7 of asynchronous serial interface operation mode register (asim6) txe6: bit 6 of asynchronous serial interface operation mode register (asim6) www..net
chapter 11 serial interface uart6 preliminary user?s manual u16898ej1v0ud 200 (e) normal reception reception is enabled and the r x d6 pin input is sampled when bit 7 (power6) of asynchronous serial interface operation mode register 6 (asim6) is set to 1 and then bit 5 (rxe6) of asim6 is set to 1. the 8-bit counter of the baud rate generator st arts counting when the falling edge of the r x d6 pin input is detected. when the set value of baud rate generator control register 6 (brgc6) has been counted, the r x d6 pin input is sampled again ( in figure 11-19). if the r x d6 pin is low level at this time, it is recognized as a start bit. when the start bit is detected, receptio n is started, and serial data is sequ entially stored in the receive shift register (rxs6) at the set baud rate. when the stop bi t has been received, the reception completion interrupt (intsr6) is generated and the data of rxs6 is written to receive buffer register 6 (rxb6). if an overrun error (ove6) occurs, however, the receiv e data is not written to rxb6. even if a parity error (pe6) occurs while reception is in progress, reception continues to the reception position of the stop bit, and an error interrupt (intsr6 /intsre6) is generated on completion of reception. figure 11-19. reception completi on interrupt request timing r x d6 (input) intsr6 start d0 d1 d2 d3 d4 d5 d6 d7 parity rxb6 stop cautions 1. be sure to read receive buffer register 6 (rxb6) e ven if a reception error occurs. otherwise, an overrun error wil l occur when the next data is received, and the reception error status will persist. 2. reception is always performed with the ? number of stop bits = 1?. the second stop bit is ignored. 3. be sure to read asynchro nous serial interface reception e rror status register 6 (asis6) before reading rxb6. www..net
chapter 11 serial interface uart6 preliminary user?s manual u16898ej1v0ud 201 (f) reception error three types of errors may occur during reception: a parity error, framing error, or ov errun error. if the error flag of asynchronous serial interface reception error st atus register 6 (asis6) is set as a result of data reception, a reception error interrupt r equest (intsr6/intsre6) is generated. which error has occurred during reception can be identifi ed by reading the contents of asis6 in the reception error interrupt servicing (intsr6/intsre6) (see figure 11-6 ). the contents of asis6 are reset to 0 when asis6 is read. table 11-3. cause of reception error reception error cause parity error the parity specifi ed for transmission does not match the parity of the receive data. framing error stop bit is not detected. overrun error reception of the next data is completed before data is read from receive buffer register 6 (rxb6). the error interrupt can be separated into reception completion interrupt (intsr6) and error interrupt (intsre6) by clearing bit 0 (isrm6) of asynchronous se rial interface operation mode register 6 (asim6) to 0. figure 11-20. reception error interrupt 1. if isrm6 is cleared to 0 (reception completion in terrupt (intsr6) and erro r interrupt (intsre6) are separated) (a) no error during recepti on (b) error during reception intsr6 intsre6 intsr6 intsre6 2. if isrm6 is set to 1 (error interrupt is included in intsr6) (a) no error during recepti on (b) error during reception intsre6 intsr6 intsre6 intsr6 www..net
chapter 11 serial interface uart6 preliminary user?s manual u16898ej1v0ud 202 (g) noise filter of receive data the rxd6 signal is sampled with the base clock output by the prescaler block. if two sampled values are the same, the output of t he match detector changes, and the data is sampled as input data. because the circuit is configured as shown in figure 11- 21, the internal processing of the reception operation is delayed by two clocks from the external signal status. figure 11-21. noise filter circuit internal signal b internal signal a match detector in base clock r x d6/p44 q in ld_en q www..net
chapter 11 serial interface uart6 preliminary user?s manual u16898ej1v0ud 203 (h) sbf transmission when the device is incorporated in lin, the sbf (syn chronous break field) transmission control function is used for transmission. for the tr ansmission operation of lin, see figure 11-1 lin transmission operation . an sbf length that is a low-level wid th of 13 bits or more is set by bits 4 to 2 (sbl62 to sbl60) of asynchronous serial interface control register 6 (asic l6). if the output width needs to be adjusted more accurately, use the baud rate value of the normal uart transmission function. [setting method] transmit 00h by setting the number of character bits of the data to 8 bits and the parity bit to 0 parity or even parity. this enables a low-level transmi ssion of a data frame consisting of 10 bits (1 bit (start bit) + 8 bits (character bits) + 1 bit (parity bit)). adjust the baud rate value to adjust this 10-bit low level to the targeted 13-bit sbf length (sbl62, sbl61, sbl60 = 1, 0, 1). example if lin is to be transmitted under the following conditions ? base clock of uart6 = 5 mhz (set by clock selection register 6 (cksr6)) ? target baud rate value = 19200 bps to realize the above baud rate value, the length of a 13-bit sbf is as follows if the baud rate generator control register 6 (brgc6) is set to 130. ? 13-bit sbf length = 0.2 s 130 2 13 = 676 s to realize a 13-bit sbf length in 10 bits, set a value 1.3 times the targeted baud rate to brgc6. in this example, set 169 to brgc6. the transmission length of a 10-bit low level in this case is as follows, and matches the 13-bit sbf length. ? 10-bit low-level transmission length = 0.2 s 169 2 10 = 676 s if the number of bits set by brgc6 runs short, adjus t the number of bits by setting the base clock of uart6. www..net
chapter 11 serial interface uart6 preliminary user?s manual u16898ej1v0ud 204 figure 11-22. example of setting proced ure of sbf transmission (flowchart) start read brgc6 register and save current set value of brgc6 register to general- purpose register. clear txe6 and rxe6 bits of asim6 register to 0 (to disable transmission/ reception). set value to brgc6 register to realize desired sbf length. set character length of data to 8 bits and parity to 0 or even using asim6 register. set txe6 bit of asim6 register to 1 to enable transmission. set sbtt6 bit to 1, and set txb6 register to ? 00h ? to start transmission. intst6 occurred? no yes clear txe6 and rxe6 bits of asim6 register to 0. (sbtt6 bit is automatically cleared.) rewrite saved brgc6 value to brgc6 register. re-set ps61 bit, ps60 bit, and cl6 bit of asim6 register to desired value. set txe6 bit of asim6 register to 1 to enable transmission. end figure 11-23. sbf transmission t x d6 intst6 1 2 3 4 5 6 7 8 9 10 11 12 13 stop sbtt6 remark t x d6: t x d6 pin (output) intst6: transmission completion interrupt request sbtt6: bit 5 of asynchronous serial interface control register 6 (asicl6) www..net
chapter 11 serial interface uart6 preliminary user?s manual u16898ej1v0ud 205 (i) sbf reception when the device is incorporated in lin, the sbf (syn chronous break field) reception control function is used for reception. for the re ception operation of lin, see figure 11-2 lin reception operation . reception is enabled when bit 7 (power6) of asynch ronous serial interface operation mode register 6 (asim6) is set to 1 and then bit 5 (rxe6) of asim6 is se t to 1. sbf reception is enabled when bit 6 (sbrt6) of asynchronous serial interface contro l register 6 (asicl6) is set to 1. in the sbf reception enabled status, the r x d6 pin is sampled and the start bit is detected in the same manner as the normal reception enable status. when the start bit has been detected, reception is st arted, and serial data is sequentially stored in the receive shift register 6 (rxs6) at the set baud rate. wh en the stop bit is received and if the width of sbf is 11 bits or more, a reception completion interrupt reques t (intsr6) is generated as normal processing. at this time, the sbrf6 and sbrt6 bits are automatical ly cleared, and sbf reception ends. detection of errors, such as ove6, pe6, and fe6 (bits 0 to 2 of as ynchronous serial interface reception error status register 6 (asis6)) is suppressed, and error detection processing of uart communication is not performed. in addition, data transfer between receive shift register 6 (rxs6) and receive buffer register 6 (rxb6) is not performed, and the reset value of ffh is retained. if the wi dth of sbf is 10 bits or less, an interrupt does not occur as error processing after the stop bit has been re ceived, and the sbf reception mode is restored. in this case, the sbrf6 and sbrt6 bits are not cleared. figure 11-24. sbf reception 1. normal sbf reception (stop bit is detect ed with a width of more than 10.5 bits) r x d6 sbrt6 /sbrf6 intsr6 1234567891011 2. sbf reception error (stop bit is detect ed with a width of 10.5 bits or less) r x d6 sbrt6 /sbrf6 intsr6 12345678910 ?0? remark r x d6: r x d6 pin (input) sbrt6: bit 6 of asynchronous serial interface control register 6 (asicl6) sbrf6: bit 7 of asicl6 intsr6: reception completion interrupt request www..net
chapter 11 serial interface uart6 preliminary user?s manual u16898ej1v0ud 206 11.4.3 dedicated baud rate generator the dedicated baud rate generator consists of a source clock selector and an 8-bit programmable counter, and generates a serial clock for transmission/reception of uart6. separate 8-bit counters are provided for transmission and reception. (1) configuration of ba ud rate generator ? base clock the clock selected by bits 3 to 0 (tps63 to tps60) of clock selection register 6 (cksr6) is supplied to each module when bit 7 (power6) of asynchronous serial interface operation mode register 6 (asim6) is 1. this clock is called the base clock and its frequency is called f xclk6 . the base clock is fixed to low level when power6 = 0. ? transmission counter this counter stops operation, clear ed to 0, when bit 7 (power6) or bit 6 (txe6) of asynchronous serial interface operation mode register 6 (asim6) is 0. it starts counting when power6 = 1 and txe6 = 1. the counter is cleared to 0 when the first data transmi tted is written to transmit buffer register 6 (txb6). if data are continuously transmitted, the counter is cleared to 0 agai n when one frame of data has been completely transmitted. if there is no data to be transmitted next, the counter is not cleared to 0 and continues counting until power6 or txe6 is cleared to 0. ? reception counter this counter stops operation, clear ed to 0, when bit 7 (power6) or bit 5 (rxe6) of asynchronous serial interface operation mode register 6 (asim6) is 0. it starts counting when the start bit has been detected. the counter stops operation after one frame has been received, until the next start bit is detected. www..net
chapter 11 serial interface uart6 preliminary user?s manual u16898ej1v0ud 207 figure 11-25. configuration of baud rate generator selector power6 8-bit counter match detector baud rate baud rate generator brgc6: mdl67 to mdl60 1/2 power6, txe6 (or rxe6) cksr6: tps63 to tps60 f xp f xp /2 f xp /2 2 f xp /2 3 f xp /2 4 f xp /2 5 f xp /2 6 f xp /2 7 f xp /2 8 f xp /2 9 f xp /2 10 f xp /2 11 f xclk6 remark power6: bit 7 of asynchronous serial interface operation mode register 6 (asim6) txe6: bit 6 of asim6 rxe6: bit 5 of asim6 cksr6: clock selection register 6 brgc6: baud rate generator control register 6 www..net
chapter 11 serial interface uart6 preliminary user?s manual u16898ej1v0ud 208 (2) generation of serial clock a serial clock can be generated by using clock selecti on register 6 (cksr6) and baud rate generator control register 6 (brgc6). select the clock to be input to the 8-bit counter by using bits 3 to 0 (tps63 to tps60) of cksr6. bits 7 to 0 (mdl67 to mdl60) of brgc6 can be used to select the division value of the 8-bit counter. (a) baud rate the baud rate can be calculated by the following expression. ? baud rate = [bps] f xclk6 : frequency of base clock selected by tps63 to tps60 bits of cksr6 register k: value set by mdl67 to mdl60 bits of br gc6 register (k = 8, 9, 10, ..., 255) (b) error of baud rate the baud rate error can be calculated by the following expression. ? error (%) = ? 1 100 [%] cautions 1. keep the baud rate error during transmission to within the permissible error range at the reception destination. 2. make sure that the baud rate error dur ing reception satisfies the range shown in (4) permissible baud rate ra nge during reception. example: frequency of base clock = 10 mhz = 10,000,000 hz set value of mdl67 to mdl60 bits of brgc6 register = 00100001b (k = 33) target baud rate = 153600 bps baud rate = 10 m/(2 33) = 10000000/(2 33) = 151,515 [bps] error = (151515/153600 ? 1) 100 = ? 1.357 [%] actual baud rate (baud rate with error) desired baud rate (correct baud rate) f xclk6 2 k www..net
chapter 11 serial interface uart6 preliminary user?s manual u16898ej1v0ud 209 (3) example of setting baud rate table 11-4. set data of baud rate generator f xp = 10.0 mhz f xp = 8.0 mhz f xp = 4.19 mhz baud rate [bps] tps63 to tps60 k calculated value err[%] tps63 to tps60 k calculated value err[%] tps63 to tps60 k calculated value err[%] 600 6h 130 601 0.16 6h 104 601 0.16 5h 109 601 0.11 1200 5h 130 1202 0.16 5h 104 1202 0.16 4h 109 1201 0.11 2400 4h 130 2404 0.16 4h 104 2404 0.16 3h 109 2403 0.11 4800 3h 130 4808 0.16 3h 104 4808 0.16 2h 109 4805 0.11 9600 2h 130 9615 0.16 2h 104 9615 0.16 1h 109 9610 0.11 10400 2h 120 10417 0.16 2h 96 10417 0.16 1h 101 10475 ? 0.28 19200 1h 130 19231 0.16 1h 104 19231 0.16 0h 109 19220 0.11 31250 1h 80 31250 0.00 0h 128 31250 0.00 0h 67 31268 0.06 38400 0h 130 38462 0.16 0h 104 38462 0.16 0h 55 38090 ? 0.80 76800 0h 65 76923 0.16 0h 52 76923 0.16 0h 27 77593 1.03 115200 0h 43 116279 0.94 0h 35 114286 ? 0.79 0h 18 116389 1.03 153600 0h 33 151515 ? 1.36 0h 26 153846 0.16 0h 14 149643 ? 2.58 230400 0h 22 227272 ? 1.36 0h 17 235294 2.12 0h 9 232778 1.03 remark tps63 to tps60: bits 3 to 0 of clock select ion register 6 (cksr6) (setting of base clock (f xclk6 )) k: value set by mdl67 to mdl60 bits of baud rate generator control register 6 (brgc6) (k = 8, 9, 10, ..., 255) f xp : oscillation frequency of clock to peripheral hardware err: baud rate error www..net
chapter 11 serial interface uart6 preliminary user?s manual u16898ej1v0ud 210 (4) permissible baud rate range during reception the permissible error from the baud rate at the trans mission destination during reception is shown below. caution make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below. figure 11-26. permissible baud rate range during reception fl 1 data frame (11 fl) flmin flmax data frame length of uart6 start bit bit 0 bit 1 bit 7 parity bit minimum permissible data frame length maximum permissible data frame length stop bit start bit bit 0 bit 1 bit 7 parity bit latch timing stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit as shown in figure 11-26, the latch timing of the re ceive data is determined by t he counter set by baud rate generator control register 6 (brgc6) a fter the start bit has been detected. if the last data (stop bit) meets this latch timing, the data can be correctly received. assuming that 11-bit data is received, the theoretical values can be calculated as follows. fl = (brate) ? 1 brate: baud rate of uart6 k: set value of brgc6 fl: 1-bit data length margin of latch timing: 2 clocks www..net
chapter 11 serial interface uart6 preliminary user?s manual u16898ej1v0ud 211 minimum permissible data frame length: flmin = 11 fl ? fl = fl therefore, the maximum receivable baud rate at the transmission destination is as follows. brmax = (flmin/11) ? 1 = brate similarly, the maximum permissible data fr ame length can be calculated as follows. 10 k + 2 21k ? 2 11 2 k 2 k flmax = fl 11 therefore, the minimum receivable baud rate at the transmission destination is as follows. brmin = (flmax/11) ? 1 = brate the permissible baud rate error between uart6 and the transmission destination can be calculated from the above minimum and maximum baud rate expressions, as follows. table 11-5. maximum/minimum permissible baud rate error division ratio (k) maximum perm issible baud rate error minimu m permissible baud rate error 8 +3.53% ? 3.61% 20 +4.26% ? 4.31% 50 +4.56% ? 4.58% 100 +4.66% ? 4.67% 255 +4.72% ? 4.73% remarks 1. the permissible error of reception depends on the number of bits in one frame, input clock frequency, and division ratio (k). the higher t he input clock frequency and the higher the division ratio (k), the higher the permissible error. 2. k: set value of brgc6 22k 21k + 2 flmax = 11 fl ? fl = fl 21k ? 2 20k 20k 21k ? 2 k ? 2 2k 21k + 2 2k www..net
chapter 11 serial interface uart6 preliminary user?s manual u16898ej1v0ud 212 (5) data frame length during continuous transmission when data is continuously transmitted, th e data frame length from a stop bit to the next start bit is extended by two clocks of base clock from the normal value. howeve r, the result of communica tion is not affected because the timing is initialized on the recepti on side when the start bit is detected. figure 11-27. data frame length during continuous transmission start bit bit 0 bit 1 bit 7 parity bit stop bit fl 1 data frame fl fl fl fl fl fl flstp start bit of second byte start bit bit 0 where the 1-bit data length is fl, the stop bit length is flstp, and base clock frequency is f xclk6 , the following expression is satisfied. flstp = fl + 2/f xclk6 therefore, the data frame length during continuous transmission is: data frame length = 11 fl + 2/f xclk6 www..net
preliminary user?s manual u16898ej1v0ud 213 chapter 12 interrupt functions 12.1 interrupt function types all interrupts are controll ed as maskable interrupts. ? maskable interrupts these interrupts undergo mask control. if two or mo re interrupt requests are simultaneously generated, each interrupt has a predetermined priori ty as shown in table 12-1. a standby release signal is generated. there are ten internal sources and four external sources of maskable interrupts. www..net
chapter 12 interrupt functions preliminary user?s manual u16898ej1v0ud 214 12.2 interrupt sources and configuration there are a total of 14 interrupt sour ces, and up to four reset sources (see table 12-1 ). table 12-1. interrupt sources interrupt source interrupt type priority note 1 name trigger internal/ external vector table address basic configuration type note 2 1 intlvi low-voltage detection note 3 internal 0006h (a) 2 intp0 0008h 3 intp1 pin input edge detection external 000ah (b) 4 inttmh1 match between tmh1 and cmp01 (when compare register is specified) 000ch 5 inttm000 match between tm00 and cr000 (when compare register is specified) 000eh 6 inttm010 match between tm00 and cr010 (when compare register is specified) 0010h 7 intad end of a/d conversion 0012h 8 intflc end of flash memory programming internal 0014h (a) 9 intp2 0016h 10 intp3 pin input edge detection external 0018h (b) 11 inttm80 match between tm80 and cr80 001ah 12 intsre6 uart6 reception error occurrence 001ch 13 intsr6 end of uart6 reception 001eh maskable 14 intst6 end of uart6 transmission internal 0020h (a) reset reset input poc power-on-clear lvi low-voltage detection note 4 reset ? wdt wdt overflow ? 0000h ? notes 1. priority is the priority order when several maskabl e interrupt requests are generated at the same time. 1 is the highest and 14 is the lowest. 2. basic configuration types (a) and (b) correspond to (a) and (b) in figure 12-1. 3. when bit 1 (lvimd) of low-voltage detec tion register (lvim) = 0 is selected. 4. when bit 1 (lvimd) of low-voltage detec tion register (lvim) = 1 is selected. www..net
chapter 12 interrupt functions preliminary user?s manual u16898ej1v0ud 215 figure 12-1. basic configuration of interrupt function (a) internal maskable interrupt mk if ie internal bus interrupt request vector table address generator standby release signal (b) external maskable interrupt internal bus external interrupt mode register (intm0, intm1) mk if ie vector table address generator standby release signal edge detector interrupt request if: interrupt request flag ie: interrupt enable flag mk: interrupt mask flag www..net
chapter 12 interrupt functions preliminary user?s manual u16898ej1v0ud 216 12.3 interrupt function control registers the interrupt functions are controlled by the following four types of registers. interrupt request flag registers (if0, if1) interrupt mask flag registers (mk0, mk1) external interrupt mode registers (intm0, intm1) program status word (psw) table 12-2 lists interrupt requests, the correspondi ng interrupt request flags, and interrupt mask flags. table 12-2. interrupt request signals and corresponding flags interrupt request signal interrupt request flag interrupt mask flag intlvi intp0 intp1 inttmh1 inttm000 inttm010 intad intflc intp2 intp3 inttm80 intsre6 intsr6 intst6 lviif pif0 pif1 tmifh1 tmif000 tmif010 adif flif pif2 pif3 tmif80 sreif6 srif6 stif6 lvimk pmk0 pmk1 tmmkh1 tmmk000 tmmk010 admk flmk pmk2 pmk3 tmmk80 sremk6 srmk6 stmk6 www..net
chapter 12 interrupt functions preliminary user?s manual u16898ej1v0ud 217 (1) interrupt request flag registers (if0, if1) an interrupt request flag is set to 1 when the co rresponding interrupt request is issued, or when the instruction is executed. it is cleared to 0 by ex ecuting an instruction when the interrupt request is acknowledged or when a reset signal is input. if0 and if1 are set with a 1-bit or 8-bi t memory manipulation instruction. reset input clears if0 and if1 to 00h. figure 12-2. format of interrupt re quest flag registers (if0, if1) address: ffe0h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if0 adif tmif010 tmif000 tmifh1 pif1 pif0 lviif 0 address: ffe1h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if1 0 stif6 srif6 sreif6 tmif80 pif3 pif2 flif if interrupt request flag 0 no interrupt request signal has been issued. 1 an interrupt request signal has been issued; an interrupt request status. caution because p30, p31, p41, and p43 have an alternate functi on as external interrupt inputs, when the output level is changed by specifyi ng the output mode of the port function, an interrupt request flag is set. therefore, the interrupt mask flag should be set to 1 before using the output mode. www..net
chapter 12 interrupt functions preliminary user?s manual u16898ej1v0ud 218 (2) interrupt mask flag registers (mk0, mk1) the interrupt mask flag is used to enable and di sable the corresponding maskable interrupts. mk0 and mk1 are set with a 1-bit or 8-bi t memory manipulation instruction. reset input sets mk0 and mk1 to ffh. figure 12-3. format of interrupt mask flag registers (mk0, mk1) address: ffe4h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk0 admk tmmk010 tmmk000 tmmkh1 pmk1 pmk0 lvimk 1 address: ffe5h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk1 1 stmk6 srmk6 sremk6 tmmk80 pmk3 pmk2 flmk mk interrupt servicing control 0 enables interrupt servicing. 1 disables interrupt servicing. caution because p30, p31, p41, and p43 have an alternate functi on as external interrupt inputs, when the output level is changed by specifyi ng the output mode of the port function, an interrupt request flag is set. therefore, the interrupt mask flag should be set to 1 before using the output mode. www..net
chapter 12 interrupt functions preliminary user?s manual u16898ej1v0ud 219 (3) external interrupt m ode register 0 (intm0) this register is used to set the valid edge of intp0 to intp2. intm0 is set with an 8-bit memo ry manipulation instruction. reset input clears intm0 to 00h. figure 12-4. format of external in terrupt mode register 0 (intm0) address: ffech after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 intm0 es21 es20 es11 es10 es01 es00 0 0 es21 es20 intp2 valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges es11 es10 intp1 valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges es01 es00 intp0 valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges cautions 1. be sure to clear bits 0 and 1 to 0. 2. before setting the intm0 register, be su re to set the corresponding interrupt mask flag ( mk = 1) to disable interrupts. after setti ng the intm0 register, clear the interrupt request flag ( if = 0), then clear the interrupt mask flag ( mk = 0), which will enable interrupts. www..net
chapter 12 interrupt functions preliminary user?s manual u16898ej1v0ud 220 (4) external interrupt m ode register 1 (intm1) intm1 is used to specify the valid edge for intp3. intm1 is set with an 8-bit memo ry manipulation instruction. reset input clears intm1 to 00h. figure 12-5. format of external in terrupt mode register 1 (intm1) address: ffedh after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 intm1 0 0 0 0 0 0 es31 es30 es31 es30 intp3 valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges cautions 1. be sure to clear bits 2 to 7 to 0. 2. before setting intm1, set pmk3 to 1 to disable interrupts. to enable interrupts, clear pif3 to 0, then clear pmk3 to 0. (5) program status word (psw) the program status word is used to hol d the instruction executi on result and the current st atus of the interrupt requests. the ie flag, used to enable and dis able maskable interrupts, is mapped to psw. psw can be read- and write-accessed in 8-bit units, as well as using bit manipulation instructions and dedicated instructions (ei and di). when a vectored interrupt is ack nowledged, the psw is automatically saved to a stack, and the ie flag is reset to 0. reset input sets psw to 02h. figure 12-6. program status word configuration ie z 0 ac 0 0 1 cy psw symbol after reset 02h 76543210 ie 0 1 disabled enabled whether to enable/disable interrupt acknowledgment used in the execution of ordinary instructions www..net
chapter 12 interrupt functions preliminary user?s manual u16898ej1v0ud 221 12.4 interrupt servicing operation 12.4.1 maskable interrupt re quest acknowledgment operation a maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0. a vect ored interrupt request is a cknowledged in the interrupt enabled status (when the ie flag is set to 1). the time required to start the interrupt servicing afte r a maskable interrupt request has been generated is shown in table 12-3. see figures 12-8 and 12-9 for the inte rrupt request acknowledgment timing. table 12-3. time from generation of maskable interrupt request to servicing minimum time maximum time note 9 clocks 19 clocks note the wait time is maximum when an interrupt request is generated imm ediately before bt and bf instructions. remark 1 clock: (f cpu : cpu clock) when two or more maskable interrupt requests are generat ed at the same time, they are acknowledged starting from the interrupt request assigned the highest priority. a pending interrupt is acknowledged when a status in which it can be acknowledged is set. figure 12-7 shows the algorithm of interrupt request acknowledgment. when a maskable interrupt request is a cknowledged, the contents of the psw and pc are saved to the stack in that order, the ie flag is reset to 0, and the data in the vector table determined for each interrupt request is loaded to the pc, and execution branches. to return from interrupt servic ing, use the reti instruction. 1 f cpu www..net
chapter 12 interrupt functions preliminary user?s manual u16898ej1v0ud 222 figure 12-7. interrupt request acknowledgment processing algorithm start if = 1? mk = 0? ie = 1? vectored interrupt servicing yes (interrupt request generated) yes yes no no no interrupt request pending interrupt request pending if: interrupt request flag mk: interrupt mask flag ie: flag to control maskable interrupt reques t acknowledgment (1 = enable, 0 = disable) figure 12-8. interrupt request ackno wledgment timing (example of mov a, r) clock cpu interrupt mov a, r saving psw and pc, jump to interrupt servicing 8 clocks interrupt servicing program if an interrupt request flag ( if) is set before an instruction clock n (n = 4 to 10) under execution becomes n ? 1, the interrupt is acknowledged after the instruction under execution is complete . figure 12-8 shows an example of the interrupt request acknowledgment timing for an 8-bit data transfe r instruction mov a, r. since this instruction is executed for 4 clocks, if an interrupt occurs for 3 clocks after the execution starts, the interrupt acknowledgment processing is performed after the mo v a, r instruction is executed. www..net
chapter 12 interrupt functions preliminary user?s manual u16898ej1v0ud 223 figure 12-9. interrupt request ack nowledgment timing (when interrupt request flag is set at last clock during instruction execution) saving psw and pc, jump to interrupt servicing 8 clocks interrupt servicing program clock cpu interrupt nop mov a, r if an interrupt request flag ( if) is set at the last clock of the instru ction, the interrupt a cknowledgment processing starts after the next instruction is executed. figure 12-9 shows an example of the in terrupt request acknowledgment timing fo r an interrupt request flag that is set at the second clock of nop (2-clock inst ruction). in this case, the mov a, r instruction after the nop instruction is executed, and then the interrupt ack nowledgment processing is performed. caution interrupt requests will be held pending while the interrupt request flag registers (if0, if1) or interrupt mask flag register s (mk0, mk1) are being accessed. www..net
chapter 12 interrupt functions preliminary user?s manual u16898ej1v0ud 224 12.4.2 multiple interrupt servicing multiple interrupt servicing in whic h another interrupt is acknowledged while an interrupt is being serviced can be performed using a priority order system. when two or more interrupts are generated at onc e, interrupt servicing is performed according to the priority assi gned to each interrupt request in advance (see table 12-1 ). figure 12-10. example of multiple interrupts example 1. multiple interrupts are acknowledged intyy ei main processing ei intyy servicing intxx servicing reti ie = 0 intxx reti ie = 0 during interrupt intxx servicing, interrupt request int yy is acknowledged, and multiple interrupts are generated. the ei instruction is iss ued before each interrupt request acknowledgmen t, and the interrupt request acknowledgment enable state is set. example 2. multiple interrupts are not generated because interrupts are not enabled intyy ei main processing reti intyy servicing intxx servicing ie = 0 intxx reti intyy is held pending ie = 0 because interrupts are not enabled in inte rrupt intxx servicing (the ei instruct ion is not issued), interrupt request intyy is not acknowledged, and mult iple interrupts are not generated. the intyy request is held pending and acknowledged after the intxx servicing is performed. ie = 0: interrupt request acknowledgment disabled www..net
chapter 12 interrupt functions preliminary user?s manual u16898ej1v0ud 225 12.4.3 interrupt request pending some instructions may keep pending t he acknowledgment of an instruction request until the completion of the execution of the next instru ction even if the interrupt request (maskable interrupt and external interrupt) is generated during the execution. the following shows such in structions (interrupt request pending instruction). ? manipulation instruction for interr upt request flag registers (if0, if1) ? manipulation instruction for interr upt mask flag registers (mk0, mk1) www..net
preliminary user?s manual u16898ej1v0ud 226 chapter 13 standby function 13.1 standby function and configuration 13.1.1 standby function table 13-1. relationship between operat ion clocks in each operation status low-speed ring-osc oscillator note 2 status operation mode note 1 lsrstop = 0 lsrstop = 1 system clock clock supplied to peripheral hardware reset stopped stop stopped stopped halt oscillating oscillating note 3 stopped oscillating oscillating notes 1. when ?cannot be stopped? is selected fo r low-speed ring-osc by the option byte. 2. when it is selected that the low-speed ring-osc osci llator ?can be stopped by software?, oscillation of the low-speed ring-osc oscillato r can be stopped by lsrstop. 3. if the operating clock of the watchdog timer is t he low-speed ring-osc clock, the watchdog timer is stopped. caution the lsrstop setting is valid only when ?can be stopped by so ftware? is set for the low-speed ring-osc oscillator by the option byte. remark lsrstop: bit 0 of the low-sp eed ring-osc mode register (lsrcm) the standby function is de signed to reduce the operat ing current of the system. the following two modes are available. (1) halt mode halt instruction execution sets t he halt mode. in the halt mode, the cpu operation clock is stopped. oscillation of the system clock oscillator continues. if the low-speed ring-osc oscillator is operating before the halt mode is set, oscillation of the clock of the low-speed ring-osc oscillator continues (refer to table 13-1 . oscillation of the low-speed ring-osc clock (w hether it cannot be stopp ed or can be stopped by software) is set by the option byte). in this mode, th e operating current is not decreased as much as in the stop mode, but the halt mode is effective for rest arting operation immediately upon interrupt request generation and carrying out intermittent operations. www..net
chapter 13 standby function preliminary user?s manual u16898ej1v0ud 227 (2) stop mode stop instruction execution sets t he stop mode. in the stop mode , the system clock oscillator stops, stopping the whole system, thereby consider ably reducing the cpu operating current. because this mode can be cleared by an interrupt request, it enables intermittent operations to be carried out. however, select the halt mode if processing must be immediately start ed by an interrupt request when the stop mode is released because the operation stops fo r the duration of eight clocks of the low-speed ring- osc clock (because an additional wait time for stabilizi ng oscillation elapses when crystal/ceramic oscillation is used). in either of these two modes, all the contents of registers, flags and data me mory just before the standby mode is set are held. the i/o port output latches an d output buffer statuses are also held. cautions 1. when shifting to the stop mode, be su re to stop the peripheral hardware operation before executing stop instruction (exc ept the peripheral hardware th at operates on the low-speed ring-osc clock). 2. the following sequence is recommended for operating current reduction of the a/d converter when the standby function is used: first cl ear bit 7 (adcs) and bit 0 (adce) of the a/d converter mode register (adm) to 0 to stop the a/d conversion opera tion, and then execute the halt or stop instruction. 3. if the low-speed ring-osc o scillator is operating before the stop mode is set, oscillation of the low-speed ring-osc clock cannot be stopped in the stop mode (refer to table 13-1). www..net
chapter 13 standby function preliminary user?s manual u16898ej1v0ud 228 13.1.2 registers used during standby the oscillation stabilization time after the standby mode is re leased is controlled by the oscillation stabilization time select register (osts). remark for the registers that start, st op, or select the clock, see chapter 5 clock generators . (1) oscillation stabilization time select register (osts) this register is used to select oscillation stabilizatio n time of the clock supplied from the oscillator when the stop mode is released. the wait time set by osts is valid only when the crystal/ceramic oscillation clock is selected as the system clock and after the stop mode is released. if the high-speed ring-osc oscillator or external clock input is selected as the system clock source, no wait time elapses. the system clock oscillator and the osc illation stabilization time that elapses after power application or release of reset are selected by the opti on byte. for details, refer to chapter 17 option byte . osts is set by using the 8-bit memory manipulation instruction. figure 13-1. format of oscillation stabiliz ation time select register (osts) address: fff4h, after reset: undefined, r/w symbol 7 6 5 4 3 2 1 0 osts 0 0 0 0 0 0 osts1 osts0 osts1 osts0 selection of oscillation stabilization time 0 0 2 10 /f x (102.4 s) 0 1 2 12 /f x (409.6 s) 1 0 2 15 /f x (3.27 ms) 1 1 2 17 /f x (13.1 ms) cautions 1. to set and then release the stop mode , set the oscillation stabil ization time as follows. expected oscillation stab ilization time of resonator oscillation stabilization time set by osts 2. the wait time after the stop mode is released does not incl ude the time from the release of the stop mode to the start of clock oscillation (?a? in the figure below), regardless of whether stop mode was releas ed by reset input or interrupt generation. stop mode is released voltage waveform of x1 pin a 3. the oscillation stabilizati on time that elapses on power app lication or after release of reset is selected by the option byte. for details, refer to chapter 17 option byte. remarks 1. ( ): f x = 10 mhz 2. determine the oscillation stabilization time of the resonator by checking the characteristics of the resonator to be used. www..net
chapter 13 standby function preliminary user?s manual u16898ej1v0ud 229 13.2 standby function operation 13.2.1 halt mode (1) halt mode the halt mode is set by execut ing the halt instruction. the operating statuses in t he halt mode are shown below. caution because an interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set. table 13-2. operating statuses in halt mode setting of halt mode item when low-speed ring-osc oscillation continues when low-speed ring-osc oscillation stops note 1 system clock clock supply to cpu is stopped. cpu operation stops. port (latch) holds status before halt mode was set. 16-bit timer/event counter 00 operable 8-bit timer 80 operable sets count clock to f xp to f xp /2 12 operable low-speed ring-osc cannot be stopped note 2 . ? 8-bit timer h1 sets count clock to f rl /2 7 low-speed ring-osc can be stopped note 2 . operable operation stops. ?clock to peripheral hardware? selected as operating clock operation stops. low-speed ring-osc cannot be stopped note 2 . operable ? watchdog timer ?low-speed ring-osc clock? selected as operating clock low-speed ring-osc can be stopped note 2 . operation stops. a/d converter operable serial interface uart6 operable low-voltage detector operable external interrupt operable notes 1. when ?stopped by software? is selected for low- speed ring-osc by the option byte and low-speed ring- osc is stopped by software (for the option byte, see chapter 17 option byte ). 2. ?low-speed ring-osc cannot be stopped? or ?low-s peed ring-osc can be stopped by software? can be selected by the option byte. www..net
chapter 13 standby function preliminary user?s manual u16898ej1v0ud 230 (2) halt mode release the halt mode can be released by the following two sources. (a) release by unmasked interrupt request when an unmasked interrupt request is generat ed, the halt mode is released. if interrupt acknowledgement is enabled, vectored in terrupt servicing is carried out. if interrupt acknowledgement is disabled, the next address instruction is executed. figure 13-2. halt mode release by interrupt request generation halt instruction wait wait operating mode halt mode operating mode oscillation system clock oscillation status of cpu standby release signal interrupt request remarks 1. the broken lines indicate the case when the interrupt request which has released the standby mode is acknowledged. 2. the wait time is as follows: when vectored interrupt servicing is carried out: 9 or 10 clocks when vectored interrupt servicing is not carried out: 1 or 2 clocks www..net
chapter 13 standby function preliminary user?s manual u16898ej1v0ud 231 (b) release by reset input when the reset signal is input, halt mode is releas ed, and then, as in the case with a normal reset operation, the program is executed after br anching to the reset vector address. figure 13-3. halt mode release by reset input (1) when cpu clock is high-speed ring-osc clock or external input clock halt instruction reset signal system clock oscillation operation mode halt mode reset period operation mode oscillates oscillation stops oscillates cpu status operation stops note (2) when cpu clock is crys tal/ceramic oscillation clock halt instruction reset signal system clock oscillation operation mode halt mode reset period operation stops note oscillation stabilization waits oscillates oscillation stops oscillates cpu status oscillation stabilization time (2 10 /f x to 2 17 /f x ) operation mode note the operation is stopped (8/f rl + 96/f rh ) because the option byte is referenced. remark f x : system clock oscillation frequency f rl : low-speed ring-osc clock oscillation frequency f rh : high-speed ring-osc clock oscillation frequency table 13-3. operation in response to interrupt request in halt mode release source mk ie operation 0 0 next address instruction execution 0 1 interrupt servicing execution maskable interrupt request 1 halt mode held reset input ? reset processing : don?t care www..net
chapter 13 standby function preliminary user?s manual u16898ej1v0ud 232 13.2.2 stop mode (1) stop mode setting and operating statuses the stop mode is set by exec uting the stop instruction. caution because an interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set. thus, in the stop mode, the no rmal operation mode is restored after the stop instruction is execu ted and then the operation is stopped for the duration of eight low-speed ring-osc clocks (a fter an additional wait time for stabilizing oscillation set by the oscillation stabilization ti me select register (ost s) has elapsed when crystal/ceramic oscillation is used). the operating statuses in t he stop mode are shown below. table 13-4. operating statuses in stop mode setting of stop mode item when low-speed ring-osc oscillation continues when low-speed ring-osc oscillation stops note 1 system clock oscillation stops. cpu operation stops. port (latch) holds status before stop mode is set. 16-bit timer/event counter 00 operation stops. 8-bit timer 80 operation stops. sets count clock to f xp to f xp /2 12 operation stops. low-speed ring-osc cannot be stopped note 2 . ? 8-bit timer h1 sets count clock to f rl /2 7 low-speed ring-osc can be stopped note 2 . operable operation stops. ?clock to peripheral hardware? selected as operating clock operation stops. low-speed ring-osc cannot be stopped note 2 . operable ? watchdog timer ?low-speed ring-osc clock? selected as operating clock low-speed ring-osc can be stopped note 2 . operation stops. a/d converter operation stops. serial interface uart6 operation stops. low-voltage detector operable external interrupt operable notes 1. when ?stopped by software? is selected for low-sp eed ring-osc by the option byte the low-speed ring- osc is stopped by software (for the option byte, see chapter 17 option byte ). 2. ?low-speed ring-osc cannot be stopped? or ?low-s peed ring-osc can be stopped by software? can be selected by the option byte. www..net
chapter 13 standby function preliminary user?s manual u16898ej1v0ud 233 (2) stop mode release figure 13-4. operation timing wh en stop mode is released <1> if high-speed ring-osc clock or external input clock is selected as system clock to be supplied system clock oscillation cpu clock stop mode is released. stop mode high-speed ring-osc clock or external clock input operation stops (8/f rl ). <2> if crystal/ceramic oscillation clock is selected as system cl ock to be supplied system clock oscillation cpu clock stop mode is released. stop mode halt status (oscillation stabilization time set by osts) crystal/ceramic oscillation clock operation stops (8/f rl ). remark f rl : low-speed ring-osc clock oscillation frequency the stop mode can be released by the following two sources. www..net
chapter 13 standby function preliminary user?s manual u16898ej1v0ud 234 (a) release by unmasked interrupt request when an unmasked interrupt request is generated, the stop mode is released. after the oscillation stabilization time has elapsed, if interrupt acknowle dgment is enabled, vectored interrupt servicing is carried out. if interrupt acknowledgment is dis abled, the next address instruction is executed. figure 13-5. stop mode release by interrupt request generation (1) if cpu clock is high-speed ri ng-osc clock or external input clock operation mode operation mode oscillation stop instruction stop mode standby release signal system clock oscillation cpu status oscillation oscillation stops. operation stops. interrupt request (8/f rl ) (2) if cpu clock is crys tal/ceramic oscillation clock waiting for stabilization of oscillation oscillation stabilization time (set by osts) (halt mode status) operation mode operation mode oscillation stop instruction stop mode standby release signal system clock cpu status oscillation oscillation stops. operation stops. interrupt request (8/f rl ) remarks 1. the broken lines indicate the case when the interrupt request that has released the standby mode is acknowledged. 2. f rl : low-speed ring-osc clock oscillation frequency www..net
chapter 13 standby function preliminary user?s manual u16898ej1v0ud 235 (b) release by reset input when the reset signal is input, stop mode is released and a reset operation is performed after the oscillation stabilization time has elapsed. figure 13-6. stop mode release by reset input (1) if cpu clock is high-speed ri ng-osc clock or external input clock stop instruction reset signal system clock oscillation operation mode stop mode reset period operation mode oscillation oscillation stops. oscillation cpu status operation stops note . (2) if cpu clock is crys tal/ceramic oscillation clock stop instruction reset signal system clock oscillation operation mode stop mode reset period operation stops note . operation mode oscillation oscillation stops. oscillation cpu status oscillation stabilization time (2 10 /f x to 2 17 /f x ) oscillation stabilization waits note the operation is stopped (8/f rl + 96/f rh ) because the option byte is referenced. remark f x : system clock oscillation frequency f rl : low-speed ring-osc clock oscillation frequency f rh : high-speed ring-osc clock oscillation frequency table 13-5. operation in response to interrupt request in stop mode release source mk ie operation 0 0 next address instruction execution 0 1 interrupt servicing execution maskable interrupt request 1 stop mode held reset input ? reset processing : don?t care www..net
preliminary user?s manual u16898ej1v0ud 236 chapter 14 reset function the following four operations are av ailable to generate a reset signal. (1) external reset input via reset pin (2) internal reset by watchdog timer program loop detection (3) internal reset by comparison of supply voltage and detection voltage of power-on-clear (poc) circuit (4) internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (lvi) external and internal resets have no functional differences . in both cases, program ex ecution starts at the address at 0000h and 0001h when the reset signal is input. a reset is applied when a low level is input to the reset pin, the watchdog timer overflows, or by poc and lvi circuit voltage detection, and each item of hardware is set to the status show n in table 14-1. each pin is high impedance during reset input or during the oscillation stabilizati on time just after reset release, except for p130, which is low-level output. when a high level is input to the reset pin, the reset is released and program exec ution starts using the cpu clock after referencing the option byte (after the option byte is referenced and the clock oscillation stabilization time elapses if crystal/ceramic oscillation is selected). a rese t generated by the watchdog time r source is automatically released after the reset, and program execution starts using the cpu clock after referencing the option byte (after the option byte is referenced and the clock o scillation stabilization time elapses if cr ystal/ceramic oscillation is selected). (see figures 14-2 to 14-4 ). reset by poc and lvi circuit power supply detection is automatically released when v dd > v poc or v dd > v lvi after the reset, and program execution starts using the cpu clock after referencing the option byte (after the option byte is referenced and the clock oscillat ion stabilization time elapses if crystal/ceramic oscillation is selected) (see chapter 15 power-on-clear circuit and chapter 16 low-voltage detector ). cautions 1. for an external reset, input a low level for 1 s or more to the reset pin. 2. during reset input, the system clock and low-speed ring-osc cl ock stop oscillating. 3. when the reset pin is used as an input-onl y port pin (p34), the 78k0s/ka1+ is reset if a low level is input to the reset pin after reset is re leased by the poc circui t and before the option byte is referenced again. the reset status is retained until a high level is input to the reset pin. www..net
chapter 14 reset function preliminary user?s manual u16898ej1v0ud 237 figure 14-1. block di agram of reset function lvirf wdtrf reset control flag register (resf) internal bus reset signal of watchdog timer reset reset signal of power-on-clear circuit reset signal of low-voltage detector reset signal reset signal reset signal to lvim/lvis register clear set clear set caution the lvi circuit is not reset by the internal reset signal of the lvi circuit. remarks 1. lvim: low-voltage detect register 2. lvis: low-voltage detection level select register www..net
chapter 14 reset function preliminary user?s manual u16898ej1v0ud 238 figure 14-2. timing of reset by reset input <1> with high-speed ring-osc cl ock or external clock input delay hi-z note normal operation in progress cpu clock reset period (oscillation stops) normal operation (reset processing, cpu clock) reset internal reset signal port pin high-speed ring-osc clock or external clock input delay operation stops because option byte is referenced. (8/f rl + 96/f rh ) <2> with crystal/ceramic oscillation clock delay hi-z note normal operation in progress cpu clock reset period (oscillation stops) oscillation stabilization time (2 10 /f x to 2 17 /f x ) normal operation (reset processing, cpu clock) reset internal reset signal port pin crystal/ceramic oscillation clock delay operation stops because option byte is referenced. (8/f rl + 96/f rh ) note p130 outputs a low level, and the other po rt pins go into a high-impedance state. remark f x : system clock oscillation frequency f rl : low-speed ring-osc clock oscillation frequency f rh : high-speed ring-osc clock oscillation frequency www..net
chapter 14 reset function preliminary user?s manual u16898ej1v0ud 239 figure 14-3. timing of reset by overflow of watchdog timer <1> with high-speed ring-osc cl ock or external clock input hi-z note normal operation in progress cpu clock reset period (oscillation stops) normal operation (reset processing, cpu clock) internal reset signal port pin high-speed ring-osc clock or external clock input operation stops because option byte is referenced. (8/f rl + 96/f rh ) watchdog timer overflow <2> with crystal/ceramic oscillation clock hi-z note normal operation in progress cpu clock reset period (oscillation stops) oscillation stabilization time (2 10 /f x to 2 17 /f x ) normal operation (reset processing, cpu clock) internal reset signal port pin crystal/ceramic oscillation clock operation stops because option byte is referenced. (8/f rl + 96/f rh ) watchdog timer overflow note p130 outputs a low level, and the other po rt pins go into a high-impedance state. caution the watchdog timer is also reset in the case of an internal reset of the watchdog timer. remark f x : system clock oscillation frequency f rl : low-speed ring-osc clock oscillation frequency f rh : high-speed ring-osc clock oscillation frequency www..net
chapter 14 reset function preliminary user?s manual u16898ej1v0ud 240 figure 14-4. reset timing by reset input in stop mode <1> with high-speed ring-osc cl ock or external clock input delay hi-z note cpu clock reset period (oscillation stops) normal operation (reset processing, cpu clock) reset internal reset signal port pin high-speed ring-osc clock or external clock input delay operation stops because option byte is referenced. (8/f rl + 96/f rh ) normal operation in progress stop instruction is executed. stop status (oscillation stops) <2> with crystal/ceramic oscillation clock delay hi-z note normal operation in progress cpu clock reset period (oscillation stops) oscillation stabilization time (2 10 /f x to 2 17 /f x ) normal operation (reset processing, cpu clock) reset internal reset signal port pin crystal/ceramic oscillation clock delay operation stops because option byte is referenced. (8/f rl + 96/f rh ) stop instruction is executed. stop status (oscillation stops) note p130 outputs a low level, and the other po rt pins go into a high-impedance state. remarks 1. for the reset timing of the power-on-clear ci rcuit and low-voltage detector, refer to chapter 15 power-on-clear circuit and chapter 16 low-voltage detector . 2. f x : system clock oscillation frequency f rl : low-speed ring-osc clock oscillation frequency f rh : high-speed ring-osc clock oscillation frequency www..net
chapter 14 reset function preliminary user?s manual u16898ej1v0ud 241 table 14-1. hardware statuses after reset acknowledgment (1/2) hardware status after reset program counter (pc) note 1 contents of reset vector table (0000h and 0001h) are set. stack pointer (sp) undefined program status word (psw) 02h data memory undefined note 2 ram general-purpose registers undefined note 2 ports (p2 to p4, p12, p13) (output latches) 00h port mode registers (pm2 to pm4, pm12) ffh port mode control register (pmc2) 00h pull-up resistor option registers (pu2, pu3, pu4, pu12) 00h processor clock control register (pcc) 02h preprocessor clock control register (ppcc) 02h low-speed ring-osc mode register (lsrcm) 00h high-speed ring-osc mode register (hsrcm) 00h oscillation stabilization time select register (osts) undefined timer counter 00 (tm00) 0000h capture/compare registers 000, 010 (cr000, cr010) 0000h mode control register 00 (tmc00) 00h prescaler mode register 00 (prm00) 00h capture/compare control register 00 (crc00) 00h 16-bit timer 00 timer output control register 00 (toc00) 00h timer counter 80 (tm80) 00h compare register (cr80) undefined 8-bit timer 80 mode control register 80 (tmc80) 00h compare registers (cmp01, cmp11) 00h 8-bit timer h1 mode register 1 (tmhmd1) 00h mode register (wdtm) 67h watchdog timer enable register (wdte) 9ah conversion result registers (adcr, adcrh) undefined mode register (adm) 00h a/d converter analog input channel specification register (ads) 00h notes 1. only the contents of pc are undefined while reset is being input and while the oscillation stabilization time elapses. the statuses of the other hardware units remain unchanged. 2. the status after reset is held in the standby mode. www..net
chapter 14 reset function preliminary user?s manual u16898ej1v0ud 242 table 14-1. hardware statuses after reset acknowledgment (2/2) hardware status after reset receive buffer register 6 (rxb6) ffh transmit buffer register 6 (txb6) ffh asynchronous serial interface oper ation mode register 6 (asim6) 01h asynchronous serial interface rece ption error status register 6 (asis6) 00h asynchronous serial interface tran smission error status register 6 (asif6) 00h clock select register 6 (cksr6) 00h baud rate generator control register 6 (brgc6) ffh asynchronous serial interface control register 6 (asicl6) 16h serial interface uart6 input select control register (isc) 00h reset function reset control flag register (resf) 00h note low-voltage detection register (lvim) 00h note low-voltage detector low-voltage detection level select register (lvis) 00h note request flag registers (if0, if1) 00h mask flag registers (mk0, mk1) ffh interrupt external interrupt mode registers (intm0, intm1) 00h note these values change as follows depending on the reset source. reset source register reset input reset by poc reset by wdt reset by lvi resf see table 14-2 . lvim lvis cleared (00h) cleared (00h) cleared (00h) held www..net
chapter 14 reset function preliminary user?s manual u16898ej1v0ud 243 14.1 register for confirming reset source many internal reset generation sources exist in the 78k0s/ ka1+. the reset control flag register (resf) is used to store which source has generated the reset request. resf can be read by an 8-bit memory manipulation instruction. reset input, reset input by power-on-clear (poc ) circuit, and reading resf clear resf to 00h. figure 14-5. format of reset control flag register (resf) address: ff54h after reset: 00h note r symbol 7 6 5 4 3 2 1 0 resf 0 0 0 wdtrf 0 0 0 lvirf wdtrf internal reset request by watchdog timer (wdt) 0 internal reset request is not generated, or resf is cleared. 1 internal reset request is generated. lvirf internal reset request by low-voltage detector (lvi) 0 internal reset request is not generated, or resf is cleared. 1 internal reset request is generated. note the value after reset varies depending on the reset source. caution do not read data by a 1-bi t memory manipulation instruction. the status of resf when a reset request is generated is shown in table 14-2. table 14-2. resf status when reset request is generated reset source flag reset input reset by poc reset by wdt reset by lvi wdtrf set (1) held lvirf cleared (0) cleared (0) held set (1) www..net
preliminary user?s manual u16898ej1v0ud 244 chapter 15 power-on-clear circuit 15.1 functions of power-on-clear circuit the power-on-clear circuit (poc) has the following functions. ? generates internal reset signal at power on. ? compares supply voltage (v dd ) and detection voltage (v poc = 2.1 v 0.1 v), and generates internal reset signal when v dd < v poc . cautions 1. if an internal reset signal is generated in the poc circui t, the reset control flag register (resf) is cleared to 00h. 2. because the detection voltage (v poc ) of the poc circuit is in a range of 2.1 v 0.1 v, use a voltage in the range of 2.2 to 5.5 v. remark this product incorporates multiple hardware functions that generate an internal reset signal. a flag that indicates the reset cause is located in the reset cont rol flag register (resf) for when an internal reset signal is generated by the watchdog timer (wdt) or lo w-voltage-detection (lvi) circuit. resf is not cleared to 00h and the flag is set to 1 when an in ternal reset signal is generated by wdt or lvi. for details of resf, see chapter 14 reset function . www..net
chapter 15 power-on-clear circuit preliminary user?s manual u16898ej1v0ud 245 15.2 configuration of power-on-clear circuit the block diagram of the power-on-clear circuit is shown in figure 15-1. figure 15-1. block diagram of power-on-clear circuit ? + detection voltage source (v poc ) internal reset signal v dd v dd 15.3 operation of power-on-clear circuit in the power-on-clear circuit, the supply voltage (v dd ) and detection voltage (v poc = 2.1 v 0.1 v) are compared, and when v dd < v poc , an internal reset signal is generated. figure 15-2. timing of internal reset si gnal generation in powe r-on-clear circuit time supply voltage (v dd ) poc detection voltage (v poc = 2.1 v0.1v) internal reset signal www..net
chapter 15 power-on-clear circuit preliminary user?s manual u16898ej1v0ud 246 15.4 cautions for power-on-clear circuit in a system where the supply voltage (v dd ) fluctuates for a certain period in the vicinity of the poc detection voltage (v poc ), the system may be repeatedly reset and released from the reset status. in this case, the time from release of reset to the start of the oper ation of the microcontroller can be arbitrarily set by taking the following action. after releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a software counter that uses a time r, and then initialize the ports. figure 15-3. example of software pr ocessing after release of reset (1/2) ? if supply voltage fluctuation is 50 ms or le ss in vicinity of poc detection voltage power-on clear ; the r eset source (power-on clear, wdt, or lvi) can be identified by the resf register. ; tmifh1 = 1: interrupt request is generated. ; initialization of ports, etc. ; 8-bit timer h1 can operate on the low-speed ring-osc clock. source: f rl (480 khz (max.))/2 7 compare value 200 = 53 ms (f rl : low-speed ring-osc clock oscillation frequency) no note 1 reset check reset source note 2 yes 50 ms has passed? (tmifh1 = 1?) initialization processing timer starts (set to 50 ms) notes 1. if reset is generated again during this period , initialization processing is not started. 2. a flowchart is shown on the next page. www..net
chapter 15 power-on-clear circuit preliminary user?s manual u16898ej1v0ud 247 figure 15-3. example of software pr ocessing after release of reset (2/2) ? checking reset cause yes no check reset source power-on clear/external reset generated reset processing by watchdog timer reset processing by low-voltage detector no wdtrf of resf register = 1? lvirf of resf register = 1? yes www..net
preliminary user?s manual u16898ej1v0ud 248 chapter 16 low-voltage detector 16.1 functions of low-voltage detector the low-voltage detector (lvi) has following functions. ? compares supply voltage (v dd ) and detection voltage (v lvi ), and generates an internal interrupt signal or internal reset signal when v dd < v lvi . ? detection levels (ten levels) of supply voltage can be changed by software. ? interrupt or reset function can be selected by software. ? operable in stop mode. when the low-voltage detector is used to reset, bit 0 (lvirf) of the reset control flag register (resf) is set to 1 if reset occurs. for deta ils of resf, refer to chapter 14 reset function . 16.2 configuration of low-voltage detector the block diagram of the low-voltage detector is shown in figure 16-1. figure 16-1. block diagram of low-voltage detector lvion detection voltage source (v lvi ) v dd n-ch low-voltage detection level select register (lvis) low-voltage detect register (lvim) lvis2 lvimd lvif intlvi internal reset signal 4 v dd lvis1 lvis0 lvis3 low-voltage detection level selector selector internal bus + ? www..net
chapter 16 low-voltage detector preliminary user?s manual u16898ej1v0ud 249 16.3 registers controlling low-voltage detector the low-voltage detector is contro lled by the following registers. ? low-voltage detect register (lvim) ? low-voltage detection level select register (lvis) (1) low-voltage detect register (lvim) this register sets low-voltag e detection and the operation mode. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 16-2. format of low-vol tage detect register (lvim) <0> lvif <1> lvimd 2 0 3 0 4 0 5 0 6 0 <7> lvion symbol lvim address: ff50h after reset: 00h r/w note 1 lvion notes 2, 3 enabling low-voltage detection operation 0 disable operation 1 enable operation lvimd note 2 low-voltage detection operation mode selection 0 generate interrupt signal when supply voltage (v dd ) < detection voltage (v lvi ) 1 generate internal reset signal when supply voltage (v dd ) < detection voltage (v lvi ) lvif note 4 low-voltage detection flag 0 supply voltage (v dd ) > detection voltage (v lvi ), or when operation is disabled 1 supply voltage (v dd ) < detection voltage (v lvi ) notes 1. bit 0 is a read-only bit. 2. lvion, and lvimd are cleared to 0 at a reset other than an lvi reset. these are not cleared to 0 at an lvi reset. 3. when lvion is set to 1, operation of the com parator in the lvi circuit is started. use software to instigate a wait of at least 0.2 ms from when lvion is set to 1 until the voltage is confirmed at lvif. 4. the value of lvif is output as the interru pt request signal intlvi when lvion = 1 and lvimd = 0. cautions 1. to stop lvi, follow either of the procedures below. ? when using 8-bit manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvion to 0. 2. be sure to set bits 2 to 6 to 0. www..net
chapter 16 low-voltage detector preliminary user?s manual u16898ej1v0ud 250 (2) low-voltage detection l evel select register (lvis) this register selects the low-voltage detection level. this register can be set by an 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 16-3. format of low-voltage dete ction level select register (lvis) address: ff51h, after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 lvis 0 0 0 0 lvis3 lvis2 lvis1 lvis0 lvis3 lvis2 lvis1 lvis0 detection level 0 0 0 0 v lvi0 (4.3 v 0.2 v) 0 0 0 1 v lvi1 (4.1 v 0.2 v) 0 0 1 0 v lvi2 (3.9 v 0.2 v) 0 0 1 1 v lvi3 (3.7 v 0.2 v) 0 1 0 0 v lvi4 (3.5 v 0.2 v) 0 1 0 1 v lvi5 (3.3 v 0.15 v) 0 1 1 0 v lvi6 (3.1 v 0.15 v) 0 1 1 1 v lvi7 (2.85 v 0.15 v) 1 0 0 0 v lvi8 (2.6 v 0.15 v) 1 0 0 1 v lvi9 (2.35 v 0.15 v) other than above setting prohibited caution bits 4 to 7 must be set to 0. www..net
chapter 16 low-voltage detector preliminary user?s manual u16898ej1v0ud 251 16.4 operation of low-voltage detector the low-voltage detector can be us ed in the following two modes. ? used as reset compares the supply voltage (v dd ) and detection voltage (v lvi ), and generates an internal reset signal when v dd < v lvi . ? used as interrupt compares the supply voltage (v dd ) and detection voltage (v lvi ), and generates an interrupt signal (intlvi) when v dd < v lvi . the operation is set as follows. (1) when used as reset ? when starting operation <1> mask the lvi interrupt (lvimk = 1). <2> set the detection voltage using bits 3 to 0 (lvis3 to lvis0) of the low-voltage detection level select register (lvis). <3> set bit 7 (lvion) of lvim to 1 (enables lvi operation). <4> use software to instigate a wait of at least 0.2 ms. <5> wait until ?supply voltage (v dd ) > detection voltage (v lvi )? at bit 0 (lvif) of lvim is confirmed. <6> set bit 1 (lvimd) of lvim to 1 (generates internal reset signal when supply voltage (v dd ) < detection voltage (v lvi )). figure 16-4 shows the timing of generating the internal reset signal of the low-voltage detector. numbers <1> to <6> in this figure correspond to <1> to <6> above. cautions 1. <1> must always be executed. when lvimk = 0, an interrupt may occur immediately after the processing in <3>. 2. if supply voltage (v dd ) > detection voltage (v lvi ) when lvim is set to 1, an internal reset signal is not generated. ? when stopping operation either of the following pr ocedures must be executed. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvimd to 0 and lvion to 0 in that order. www..net
chapter 16 low-voltage detector preliminary user?s manual u16898ej1v0ud 252 figure 16-4. timing of low-voltage dete ctor internal reset signal generation supply voltage (v dd ) lvi detection voltage (v lvi ) poc detection voltage (v poc ) lvif flag lvirf flag note lvi reset signal poc reset signal internal reset signal cleared by software not cleared not cleared not cleared not cleared cleared by software <2> <1> <3> <5> <6> time clear clear clear <4> 0.2 ms or longer lvimk flag (set by software) lvion flag (set by software) lvimd flag (set by software) note lvirf is bit 0 of the reset control flag regi ster (resf). for details of resf, refer to chapter 14 reset function . remark <1> to <6> in figure 16-4 above correspond to <1> to <6> in the description of ?when starting operation? in 16.4 (1) when used as reset . www..net
chapter 16 low-voltage detector preliminary user?s manual u16898ej1v0ud 253 (2) when used as interrupt ? when starting operation <1> mask the lvi interrupt (lvimk = 1). <2> set the detection voltage using bits 3 to 0 (lvis3 to lvis0) of the low-voltage detection level select register (lvis). <3> set bit 7 (lvion) of lvim to 1 (enables lvi operation). <4> use software to instigate a wait of at least 0.2 ms. <5> wait until ?supply voltage (v dd ) > detection voltage (v lvi )? at bit 0 (lvif) of lvim is confirmed. <6> clear the interrupt request flag of lvi (lviif) to 0. <7> release the interrupt mask flag of lvi (lvimk). <8> execute the ei instruction (w hen vector interrupts are used). figure 16-5 shows the timing of generat ing the interrupt signal of the low- voltage detector. numbers <1> to <7> in this figure correspond to <1> to <7> above. ? when stopping operation either of the following pr ocedures must be executed. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvion to 0. figure 16-5. timing of low-voltage detector interrupt signal generation supply voltage (v dd ) lvi detection voltage (v lvi ) poc detection voltage (v poc ) time lvif flag intlvi lviif flag internal reset signal <2> <1> <3> <5> <6> cleared by software <7> cleared by software <4> 0.2 ms or longer lvimk flag (set by software) lvion flag (set by software) remark <1> to <7> in figure 16-5 above correspond to <1> to <7> in the description of ?when starting operation? in 16.4 (2) when used as interrupt . www..net
chapter 16 low-voltage detector preliminary user?s manual u16898ej1v0ud 254 16.5 cautions for low-voltage detector in a system where the supply voltage (v dd ) fluctuates for a certain period in t he vicinity of the lvi detection voltage (v lvi ), the operation is as follows depending on how the low-voltage detector is used. <1> when used as reset the system may be repeatedly reset and released from the reset status. in this case, the time from release of reset to the star t of the operation of the microcontroller can be arbitrarily set by taking action (1) below. <2> when used as interrupt interrupt requests may be frequently generated. take action (2) below. in this system, take the following actions. (1) when used as reset after releasing the reset signal, wait for the supply voltage fluctuation pe riod of each system by means of a software counter that uses a time r, and then initialize the ports. www..net
chapter 16 low-voltage detector preliminary user?s manual u16898ej1v0ud 255 figure 16-6. example of software pr ocessing after release of reset (1/2) ? if supply voltage fluctuation is 50 ms or less in vicinity of lvi detection voltage yes lvi no ; the reset source (power-on clear, wdt, or lvi) can be identified by the resf register. ; tmifh1 = 1: interrupt request is generated. ; initialization of ports ; 8-bit timer h1 can operate with the low-speed ring-osc clock. source: f rl (480 khz (max.))/2 7 compare value 200 = 53 ms (f rl : low-speed ring-osc clock oscillation frequency) note 1 reset check reset source note 2 50 ms has passed? (tmifh1 = 1?) initialization processing start timer (set to 50 ms) notes 1. if reset is generated again during this period , initialization processing is not started. 2. a flowchart is shown on the next page. www..net
chapter 16 low-voltage detector preliminary user?s manual u16898ej1v0ud 256 figure 16-6. example of software pr ocessing after release of reset (2/2) ? checking reset source yes no yes no check reset source power-on-clear/external reset generated reset processing by watchdog timer reset processing by low-voltage detector wdtrf of resf register = 1? lvirf of resf register = 1? (2) when used as interrupt check that ?supply voltage (v dd ) > detection voltage (v lvi )? in the servicing routine of the lvi interrupt by using bit 0 (lvif) of the low-voltage detection register (lvim). clear bit 1 (lviif) of interrupt request flag register 0 (if0) to 0 and enable interrupts (ei). in a system where the supply voltage fluc tuation period is long in the vicinity of the lvi detection voltage, wait for the supply voltage fluctuation peri od, check that ?supply voltage (v dd ) > detection voltage (v lvi )? using the lvif flag, and then enable interrupts (ei). www..net
preliminary user?s manual u16898ej1v0ud 257 chapter 17 option byte the 78k0s/ka1+ has an area called an option byte at ad dress 0080h of the flash memory. when using the product, be sure to set the following functions by using the option byte. 1. selection of system clock source ? high-speed ring-osc clock ? crystal/ceramic oscillation clock ? external clock input 2. low-speed ring-osc clock oscillation ? cannot be stopped. ? can be stopped by software. 3. control of reset pin ? used as reset pin ? reset pin is used as an input port pin (p34). 4. oscillation stabilization time on power application or reset input ? 2 10 /f x ? 2 12 /f x ? 2 15 /f x ? 2 17 /f x figure 17-1. positioning of option byte option byte oscsel1 rmce 1 1 flash memory (2048/4096 8 bits) 07ffh/0fffh 0000h 0080h def osts1 oscsel0 ringosc def osts0 www..net
chapter 17 option byte preliminary user?s manual u16898ej1v0ud 258 figure 17-2. format of option byte (1/2) address: ff80h 7 6 5 4 3 2 1 0 1 defosts1 defosts0 1 rm ce oscsel1 oscsel0 ringosc ringosc low-speed ring-osc clock oscillation 1 cannot be stopped 0 can be stopped by software cautions 1. if it is selected that low-speed ri ng-osc clock oscillation cannot be stopped, the count clock to the watchdog timer (wdt) is fixed to low-speed ring-osc. 2. if it is selected that low-speed ring-osc can be stopped by software, supply of the count clock to wdt is stopped in the halt/stop mode, regardless of the setting of bit 0 (lsrstop) of the low-speed ring-osc mode register (lsrcm). if low-speed ring-osc is selected as the count clock to 8-bit timer h1, however, the count clock is supplied in the halt/stop mode while low-speed ring-osc operates (lsrstop = 0). oscsel1 oscsel0 selection of system clock source 0 0 crystal/ceramic oscillation clock 0 1 external clock input 1 high-speed ring-osc clock caution because the x1 and x2 pins are also used as the p121 and p122 pins, the conditions under which the x1 and x2 pins can be used as port pins differ depending on the selected system clock source. (1) high-speed ring-osc clock p121 and p122 can be used as i/o port pins. (2) crystal/ceramic oscillation clock the x1 and x2 pins cannot be used as i/o port pins because they are used as clock input pins. (3) external clock input because the x1 pin is used as an external clock input pin, p121 cannot be used as an i/o port pin. remark : don?t care rmce control of reset pin 1 reset pin is used as is. 0 reset pin is used as input port pin (p34). caution if a low level is input to the reset pin afte r reset is released by the power-on clear function and before the option byte is referenced again, the 78k0s/ka1+ is reset, and the status is held until a high level is input to the reset pin. www..net
chapter 17 option byte preliminary user?s manual u16898ej1v0ud 259 figure 17-2. format of option byte (2/2) defosts1 defosts0 oscillation stabilization time on power application or reset input 0 0 2 10 /fx (102.4 s) 0 1 2 12 /fx (409.6 s) 1 0 2 15 /fx (3.27 ms) 1 1 2 17 /fx (13.1 ms) caution the setting of this option is valid only wh en the crystal/ceramic oscillation clock is selected as the system clock source. no wait time el apses if the high-speed ring-osc or external clock input is selected as the system clock source. remarks 1. ( ): f x = 10 mhz 2. for the oscillation stabilization time of the resonat or, refer to the characteristics of the resonator to be used. www..net
preliminary user?s manual u16898ej1v0ud 260 chapter 18 flash memory flash memory versions are commonly used in the following development environments and mass production applications. { for altering software after the 78k0s/ ka1+ is soldered onto the target system. { for data adjustment when starting mass production. { for differentiating software according to the specif ication in small scale production of various models. { for facilitating inventory management. { for updating software after shipment. caution for the electrical specifications related to the flash memory rewriting, refer to chapter 20 electrical specifications (target values). 18.1 features { capacity: 4 kb/2 kb { write voltage: erase/write with a single power supply { rewriting method ? rewriting by communication with dedicated flash programmer via serial interface (on-board/off-board programming) ? rewriting flash memory by user program (self programming) { flash memory write prohibit f unction supported (security function) www..net
chapter 18 flash memory preliminary user?s manual u16898ej1v0ud 261 18.2 memory configuration the 4/2 kb internal flash memory area is divided into 16 /8 blocks and can be programmed/erased in block units. all the blocks can also be erased at once. figure 18-1. flash memory mapping special function resister (256 bytes) internal high-speed ram (128/256 bytes) use prohibited flash memory (2/4 kb) ffffh ff00h feffh 0000h 0000h 0100h 00ffh block 0 (256 bytes) block 1 (256 bytes) block 2 (256 bytes) block 3 (256 bytes) block 4 (256 bytes) block 5 (256 bytes) block 6 (256 bytes) block 7 (256 bytes) block 0 (256 bytes) block 1 (256 bytes) block 2 (256 bytes) block 3 (256 bytes) block 4 (256 bytes) block 5 (256 bytes) block 6 (256 bytes) block 7 (256 bytes) block 8 (256 bytes) block 9 (256 bytes) block 10 (256 bytes) block 11 (256 bytes) block 12 (256 bytes) block 13 (256 bytes) block 14 (256 bytes) block 15 (256 bytes) 2 kb 4 kb 0200h 01ffh 0300h 02ffh 0400h 03ffh 0500h 04ffh 0600h 05ffh 0700h 06ffh 0800h 07ffh 0900h 08ffh 0a00h 09ffh 0b00h 0affh 0c00h 0bffh 0d00h 0cffh 0e00h 0dffh 0f00h 0effh 0fffh www..net
chapter 18 flash memory preliminary user?s manual u16898ej1v0ud 262 18.3 functional outline the internal flash memory of the 78k0s/ka1+ can be rewrit ten by using the rewrite function of the dedicated flash programmer, regardless of whether the 78k0s/ka1+ has already been mounted on the target system or not (on- board/off-board programming). in addition, a security function that prohi bits rewriting the user program written to the internal flash memory is also supported, so that the program c annot be changed by an unauthorized person. the rewrite function using the user program (self programmi ng) is ideal for an application where it is assumed that the program is changed after production/ shipment of the target system. table 18-1. rewrite method rewrite method functional outline operation mode on-board programming flash memory can be rewritten after the device is mounted on the target system, by using a dedicated flash programmer. off-board programming flash memory can be rewritten before the device is mounted on the target system, by using a dedicated flash programmer and a dedicated program adapter board (fa series). flash memory programming mode self programming flash memory can be rewritten by executing a user program that has been written to the flash memory in advance by means of on-board/off- board programming. normal operation mode remark the fa series is a product of na ito densei machida mfg. co., ltd. www..net
chapter 18 flash memory preliminary user?s manual u16898ej1v0ud 263 table 18-2. basic functions support ( { : supported, : not supported) function functional outline on-board/off-board programming self programming block erasure the contents of specified memory blocks are erased. { { chip erasure the contents of the entire memory area are erased all at once. { write writing to specified addresses, and a verify check to see if write level is secured are performed. { { checksum data read from the flash memory is compared with data transferred from the flash programmer. { security setting use of the block erase command, chip erase command, and program command can be prohibited. { (only values set by on- board/off-board programming can be retained) the following table lists the security functions. the bl ock erase command prohibit, chip erase command prohibit, and program command prohibit functions are enabled by default after shipment, and security can be set by rewriting via on-board/off-board programming. each security function can be used in combination with the others at the same time. table 18-3. security functions rewriting operation when prohibited ( { : executable, : not executable) function function outline on-board/off-board programming self programming block erase command prohibit execution of a block erase command on all blocks is prohibited. setting of prohibition can be initialized by execution of a chip erase command. block erase command: chip erase command: { program command: { chip erase command prohibit execution of block erase and chip erase commands on all the blocks is prohibited. once prohibition is set, setting of prohibition cannot be initialized because the chip erase command cannot be executed. block erase command: chip erase command: program command: { program command prohibit write and block erase commands on all the blocks are prohibited. setting of prohibition can be initialized by execution of the chip erase command. block erase command: chip erase command: { program command: can always be rewritten regardless of setting of prohibition www..net
chapter 18 flash memory preliminary user?s manual u16898ej1v0ud 264 18.4 writing with flash programmer data can be written to the flash memory on-board or off-board, by using a dedicated flash programmer. (1) on-board programming the contents of the flash memory c an be rewritten after the 78k0s/ka1+ has been mounted on the target system. the connectors that connect the dedicated flash programmer must be mounted on the target system. (2) off-board programming data can be written to the flash memory with a dedicat ed program adapter (fa series ) before the 78k0s/ka1+ is mounted on the target system. remark the fa series is a product of na ito densei machida mfg. co., ltd. table 18-4. wiring between 78k0s/k a1+ and dedicated flash programmer pin configuration of dedicated flash pr ogrammer pin configuration of 78k0s/ka1+ pin name i/o pin function pin name pin no. clk note output clock to 78k0s/ka1+ flmd0 note output on-board mode signal x1 2 rxd note input receive signal txd note output receive signal/on-board mode signal x2 3 /reset output reset signal reset 6 v dd i/o v dd voltage generation v dd 5 gnd ? ground v ss 1 note in the 78k0s/ka1+, the clk and flmd0 signals are co nnected to the x1 pin and the rxd and txd signals to the x2 signal; therefore, these signals need to be directly connected. however, the dedicated flash programmer provides a dedicated adapter for the 78k 0s/ka1+, so signals do not need to be internally connected. therefore, connect the x1 or x2 pin on- board to either one of the corresponding signal lines. www..net
chapter 18 flash memory preliminary user?s manual u16898ej1v0ud 265 examples of the recommended connection when using the adapter for flash memory writing are shown below. figure 18-2. example of wiring ad apter for flash memory writing 18 17 16 20 19 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 vdd2 vdd gnd si so sck clk /reset vpp writer interface reserve/hs flash vdd (2.7 to 5.5 v) gnd rfu3 rfu2 rfu1 vde flmd1 flmd0 www..net
chapter 18 flash memory preliminary user?s manual u16898ej1v0ud 266 18.5 programming environment the environment required for writing a program to the flash memory is illustrated below. figure 18-3. environment for wr iting program to flash memory rs-232c host machine 78k0s/ka1+ v dd v ss reset dgclk note dgdata note dedicated flash programmer usb pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx x x x y y y x xx xx xx xx xx x xxx x x x x y y y y statve note dgclk and dgdata are single-wire bidirectional communication interfaces. they use uart as the communication mode. a host machine that controls the dedic ated flash programmer is necessary. uart is used for manipulation such as writing and erasing when inte rfacing between the dedicated flash programmer and the 78k0s/ka1+. to write the flash memory off-board, a dedicated program adapter (fa series) is necessary. 18.6 communication mode communication between the dedicated flash programmer and the 78k0s/ka1+ is established by serial communication via uart using the x1 or x2 pin of the 78k0s/ka1+. ? transfer rate: 115200 bps figure 18-4. communication with dedicated flash programmer 78k0s/ka1+ v dd v ss reset v dd gnd /reset x1 clk flmd0 dedicated flash programmer pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx xxx yyy x x x x x x x x x x x x x x x xxxx yyyy statve x2 rxd txd www..net
chapter 18 flash memory preliminary user?s manual u16898ej1v0ud 267 18.7 processing of pins on board to write the flash memory on-board, connectors that connect the dedicated flash programmer must be provided on the target system. first provide a f unction that selects the no rmal operation mode or flash memory programming mode on the board. when the flash memory programming mode is set, all the pins not used for programming the flash memory are in the same status as immediately after re set. therefore, if the external device does not recognize the state immediately after reset, the pins must be processed as described below. 18.7.1 x1 and x2 pins the x1 and x2 pins are used as the se rial interface of flash memory progra mming. therefore, if the x1 and x2 pins are connected to an external devic e, a signal conflict occurs. to prev ent the conflict of signals, isolate the connection with the external device. 18.7.2 reset pin if the reset signal of the dedicated flash programmer is co nnected to the reset pin that is connected to the reset signal generator on the board, signal collision takes place. to prevent this collision, isolate the connection with the reset signal generator. if the reset signal is input from the user system whil e the flash memory programming mode is set, the flash memory will not be correctly programmed. do not input any signal other than the reset signal of the dedicated flash programmer. figure 18-5. signal collision (reset pin) reset dedicated flash programmer connection signal reset signal generator signal collision output pin in the flash memory programming mode, the signal output by the reset signal generator collides with the signal output by the dedicated flash programmer. therefore, isolate the signal of the reset signal generator. 78k0s/ka1+ 18.7.3 port pins when the flash memory programming mode is set, all the pins not used for flash memory programming enter the same status as that immediately after reset. if exter nal devices connected to the ports do not recognize the port status immediately after reset, the port pin must be connected to v dd or v ss via a resistor. 18.7.4 power supply connect the v dd pin to v dd of the flash programmer, and the v ss pin to v ss of the flash programmer. supply av ref with the same power supply as that in the normal operation mode. www..net
chapter 18 flash memory preliminary user?s manual u16898ej1v0ud 268 18.8 programming method 18.8.1 controlling flash memory the following figure illustrates the proc edure to manipulate the flash memory. figure 18-6. flash memory manipulation procedure start manipulate flash memory end? yes no end flash memory programming mode is set www..net
chapter 18 flash memory preliminary user?s manual u16898ej1v0ud 269 18.8.2 flash memory programming mode to rewrite the contents of the flash memory by using the dedicated flash programmer, set the 78k0s/ka1+ in the flash memory programming mode. when the 78k0s /ka1+ is connected to the flash programmer and a communication command is transmitted to the microcontrolle r, the microcontroller is set in the flash memory programming mode. change the mode by using a jumper when writing the flash memory on-board. 18.8.3 communication commands the 78k0s/ka1+ communicates with the dedicated flash progr ammer by using commands. the signals sent from the flash programmer to the 78k0s/ka1+ are called comm ands, and the commands sent from the 78k0s/ka1+ to the dedicated flash programmer are called response commands. figure 18-7. communication commands 78k0s/ka1+ command response command dedicated flash p ro g rammer pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx xxx yyy x x x x x x x x x x x x x x x xxxx yyyy statve the flash memory control commands of the 78k0s/ka1+ are listed in the t able below. all these commands are issued from the programmer and the 78k0s/ka1+ perform pr ocessing corresponding to the respective commands. table 18-5. flash memory control commands classification command name function batch erase command erases the c ontents of the entire memory erase block erase command erases the contents of the memory of the specified block write write command writes to the specified address range and executes a verify check of the contents. checksum checksum command reads the checksum of the specified address range and compares with the written data. security security set command prohibits chip erase command, block erase command, and write command to prevent operation by third parties. the 78k0s/ka1+ returns a response command for the comm and issued by the dedicated flash programmer. the response commands sent from the 78k0s/ka1+ are listed below. table 18-6. response commands command name function ack acknowledges command/data. nak acknowledges illegal command/data. www..net
chapter 18 flash memory preliminary user?s manual u16898ej1v0ud 270 18.9 flash memory programming by self writing the 78k0s/ka1+ supports a self progra mming function that can be used to rewrite the flash memory via a user program, making it possible to upgrade programs in the field. cautions 1. self programming processing must have b een implemented before performing self writing. 2. temporarily store the data to be re written in the internal high-speed ram. 3. switch the cpu clock to high-speed ring-osc when executing self programming. 4. interrupt processing cannot be used while self programmi ng is in progress. www..net
preliminary user?s manual u16898ej1v0ud 271 chapter 19 instruction set overview this chapter lists the instruction set of the 78k0s/ka1+. for details of the operation and machine language (instruction code) of each instruction, refer to 78k/0s series instructions user?s manual (u11047e) . 19.1 operation 19.1.1 operand identifier s and description methods operands are described in ?operand? column of each inst ruction in accordance with th e description method of the instruction operand identifier (refer to the assembler spec ifications for details). when there are two or more description methods, select one of them. uppercase lette rs and the symbols #, !, $, and [ ] are key words and are described as they are. each symbol has the following meaning. ? #: immediate data specification ? !: absolute address specification ? $: relative address specification ? [ ]: indirect address specification in the case of immediate data, describe an appropriate nu meric value or a label. when using a label, be sure to describe the #, !, $ and [ ] symbols. for operand register identifiers, r and rp, either function names (x, a, c, etc.) or absolute names (names in parentheses in the table below, r0, r1 , r2, etc.) can be used for description. table 19-1. operand identifi ers and description methods identifier description method r rp sfr x (r0), a (r1), c (r2), b (r3), e (r4), d (r5), l (r6), h (r7) ax (rp0), bc (rp1), de (rp2), hl (rp3) special function register symbol saddr saddrp fe20h to ff1fh immediate data or labels fe20h to ff1fh immediate data or labels (even addresses only) addr16 addr5 0000h to ffffh immediate data or labels (only ev en addresses for 16-bit data transfer instructions) 0040h to 007fh immediate data or labels (even addresses only) word byte bit 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label remark for symbols of special function registers, see table 4-3 special function registers . www..net
chapter 19 instruction set overview preliminary user?s manual u16898ej1v0ud 272 19.1.2 description of ?operation? column a: a register; 8-bit accumulator x: x register b: b register c: c register d: d register e: e register h: h register l: l register ax: ax register pair; 16-bit accumulator bc: bc register pair de: de register pair hl: hl register pair pc: program counter sp: stack pointer psw: program status word cy: carry flag ac: auxiliary carry flag z: zero flag ie: interrupt request enable flag nmis: flag indicating non-maskable interrupt servicing in progress ( ): memory contents indicated by addre ss or register contents in parentheses h , l : higher 8 bits and lower 8 bits of 16-bit register : logical product (and) : logical sum (or) : exclusive logical sum (exclusive or) ? : inverted data addr16: 16-bit immediate data or label jdisp8: signed 8-bit data (displacement value) 19.1.3 description of ?flag? column (blank): unchanged 0: cleared to 0 1: set to 1 : set/cleared according to the result r: previously saved value is stored www..net
chapter 19 instruction set overview preliminary user?s manual u16898ej1v0ud 273 19.2 operation list flag mnemonic operand byte s clocks operation z ac cy r, #byte 3 6 r byte saddr, #byte 3 6 (saddr) byte sfr, #byte 3 6 sfr byte a, r note 1 2 4 a r r, a note 1 2 4 r a a, saddr 2 4 a (saddr) saddr, a 2 4 (saddr) a a, sfr 2 4 a sfr sfr, a 2 4 sfr a a, !addr16 3 8 a (addr16) !addr16, a 3 8 (addr16) a psw, #byte 3 6 psw byte a, psw 2 4 a psw psw, a 2 4 psw a a, [de] 1 6 a (de) [de], a 1 6 (de) a a, [hl] 1 6 a (hl) [hl], a 1 6 (hl) a a, [hl + byte] 2 6 a (hl + byte) mov [hl + byte], a 2 6 (hl + byte) a a, x 1 4 a ? x a, r note 2 2 6 a ? r a, saddr 2 6 a ? (saddr) a, sfr 2 6 a ? sfr a, [de] 1 8 a ? (de) a, [hl] 1 8 a ? (hl) xch a, [hl, byte] 2 8 a ? (hl + byte) notes 1. except r = a. 2. except r = a, x. remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). www..net
chapter 19 instruction set overview preliminary user?s manual u16898ej1v0ud 274 flag mnemonic operand byte s clocks operation z ac cy rp, #word 3 6 rp word ax, saddrp 2 6 ax (saddrp) saddrp, ax 2 8 (saddrp) ax ax, rp note 1 4 ax rp movw rp, ax note 1 4 rp ax xchw ax, rp note 1 8 ax ? rp a, #byte 2 4 a, cy a + byte saddr, #byte 3 6 (saddr), cy (saddr) + byte a, r 2 4 a, cy a + r a, saddr 2 4 a, cy a + (saddr) a, !addr16 3 8 a, cy a + (addr16) a, [hl] 1 6 a, cy a + (hl) add a, [hl + byte] 2 6 a, cy a + (hl + byte) a, #byte 2 4 a, cy a + byte + cy saddr, #byte 3 6 (saddr), cy (saddr) + byte + cy a, r 2 4 a, cy a + r + cy a, saddr 2 4 a, cy a + (saddr) + cy a, !addr16 3 8 a, cy a + (addr16) + cy a, [hl] 1 6 a, cy a + (hl) + cy addc a, [hl + byte] 2 6 a, cy a + (hl + byte) + cy a, #byte 2 4 a, cy a ? byte saddr, #byte 3 6 (saddr), cy (saddr) ? byte a, r 2 4 a, cy a ? r a, saddr 2 4 a, cy a ? (saddr) a, !addr16 3 8 a, cy a ? (addr16) a, [hl] 1 6 a, cy a ? (hl) sub a, [hl + byte] 2 6 a, cy a ? (hl + byte) note only when rp = bc, de, or hl. remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). www..net
chapter 19 instruction set overview preliminary user?s manual u16898ej1v0ud 275 flag mnemonic operand byte s clocks operation z ac cy a, #byte 2 4 a, cy a ? byte ? cy saddr, #byte 3 6 (saddr), cy (saddr) ? byte ? cy a, r 2 4 a, cy a ? r ? cy a, saddr 2 4 a, cy a ? (saddr) ? cy a, !addr16 3 8 a, cy a ? (addr16) ? cy a, [hl] 1 6 a, cy a ? (hl) ? cy subc a, [hl + byte] 2 6 a, cy a ? (hl + byte) ? cy a, #byte 2 4 a a byte saddr, #byte 3 6 (saddr) (saddr) byte a, r 2 4 a a r a, saddr 2 4 a a (saddr) a, !addr16 3 8 a a (addr16) a, [hl] 1 6 a a (hl) and a, [hl + byte] 2 6 a a (hl + byte) a, #byte 2 4 a a byte saddr, #byte 3 6 (saddr) (saddr) byte a, r 2 4 a a r a, saddr 2 4 a a (saddr) a, !addr16 3 8 a a (addr16) a, [hl] 1 6 a a (hl) or a, [hl + byte] 2 6 a a (hl + byte) a, #byte 2 4 a a byte saddr, #byte 3 6 (saddr) (saddr) byte a, r 2 4 a a r a, saddr 2 4 a a (saddr) a, !addr16 3 8 a a (addr16) a, [hl] 1 6 a a (hl) xor a, [hl + byte] 2 6 a a (hl + byte) remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). www..net
chapter 19 instruction set overview preliminary user?s manual u16898ej1v0ud 276 flag mnemonic operand byte s clocks operation z ac cy a, #byte 2 4 a ? byte saddr, #byte 3 6 (saddr) ? byte a, r 2 4 a ? r a, saddr 2 4 a ? (saddr) a, !addr16 3 8 a ? (addr16) a, [hl] 1 6 a ? (hl) cmp a, [hl + byte] 2 6 a ? (hl + byte) addw ax, #word 3 6 ax, cy ax + word subw ax, #word 3 6 ax, cy ax ? word cmpw ax, #word 3 6 ax ? word r 2 4 r r + 1 inc saddr 2 4 (saddr) (saddr) + 1 r 2 4 r r ? 1 dec saddr 2 4 (saddr) (saddr) ? 1 incw rp 1 4 rp rp + 1 decw rp 1 4 rp rp ? 1 ror a, 1 1 2 (cy, a 7 a 0 , a m ? 1 a m ) 1 rol a, 1 1 2 (cy, a 0 a 7 , a m+1 a m ) 1 rorc a, 1 1 2 (cy a 0 , a 7 cy, a m ? 1 a m ) 1 rolc a, 1 1 2 (cy a 7 , a 0 cy, a m+1 a m ) 1 saddr.bit 3 6 (saddr.bit) 1 sfr.bit 3 6 sfr.bit 1 a.bit 2 4 a.bit 1 psw.bit 3 6 psw.bit 1 set1 [hl].bit 2 10 (hl).bit 1 saddr.bit 3 6 (saddr.bit) 0 sfr.bit 3 6 sfr.bit 0 a.bit 2 4 a.bit 0 psw.bit 3 6 psw.bit 0 clr1 [hl].bit 2 10 (hl).bit 0 set1 cy 1 2 cy 1 1 clr1 cy 1 2 cy 0 0 not1 cy 1 2 cy cy remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). www..net
chapter 19 instruction set overview preliminary user?s manual u16898ej1v0ud 277 flag mnemonic operand byte s clocks operation z ac cy call !addr16 3 6 (sp ? 1) (pc + 3) h , (sp ? 2) (pc + 3) l , pc addr16, sp sp ? 2 callt [addr5] 1 8 (sp ? 1) (pc + 1) h , (sp ? 2) (pc + 1) l , pc h (00000000, addr5 + 1), pc l (00000000, addr5), sp sp ? 2 ret 1 6 pc h (sp + 1), pc l (sp), sp sp + 2 reti 1 8 pc h (sp + 1), pc l (sp), psw (sp + 2), sp sp + 3, nmis 0 r r r psw 1 2 (sp ? 1) psw, sp sp ? 1 push rp 1 4 (sp ? 1) rp h , (sp ? 2) rp l , sp sp ? 2 psw 1 4 psw (sp), sp sp + 1 r r r pop rp 1 6 rp h (sp + 1), rp l (sp), sp sp + 2 sp, ax 2 8 sp ax movw ax, sp 2 6 ax sp !addr16 3 6 pc addr16 $addr16 2 6 pc pc + 2 + jdisp8 br ax 1 6 pc h a, pc l x bc $saddr16 2 6 pc pc + 2 + jdisp8 if cy = 1 bnc $saddr16 2 6 pc pc + 2 + jdisp8 if cy = 0 bz $saddr16 2 6 pc pc + 2 + jdisp8 if z = 1 bnz $saddr16 2 6 pc pc + 2 + jdisp8 if z = 0 saddr.bit, $addr16 4 10 pc pc + 4 + jdisp8 if (saddr.bit) = 1 sfr.bit, $addr16 4 10 pc pc + 4 + jdisp8 if sfr.bit = 1 a.bit, $addr16 3 8 pc pc + 3 + jdisp8 if a.bit = 1 bt psw.bit, $addr16 4 10 pc pc + 4 + jdisp8 if psw.bit = 1 saddr.bit, $addr16 4 10 pc pc + 4 + jdisp8 if (saddr.bit) = 0 sfr.bit, $addr16 4 10 pc pc + 4 + jdisp8 if sfr.bit = 0 a.bit, $addr16 3 8 pc pc + 3 + jdisp8 if a.bit = 0 bf psw.bit, $addr16 4 10 pc pc + 4 + jdisp8 if psw.bit = 0 b, $addr16 2 6 b b ? 1, then pc pc + 2 + jdisp8 if b 0 c, $addr16 2 6 c c ? 1, then pc pc + 2 + jdisp8 if c 0 dbnz saddr, $addr16 3 8 (saddr) (saddr) ? 1, then pc pc + 3 + jdisp8 if (saddr) 0 nop 1 2 no operation ei 3 6 ie 1 (enable interrupt) di 3 6 ie 0 (disable interrupt) halt 1 2 set halt mode stop 1 2 set stop mode remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc). www..net
chapter 19 instruction set overview preliminary user?s manual u16898ej1v0ud 278 19.3 instructions listed by addressing type (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, inc, dec, ror, rol, rorc, rolc, push, pop, dbnz 2nd operand 1st operand #byte a r sfr saddr ! addr16 psw [de] [hl] [hl + byte] $addr16 1 none a add addc sub subc and or xor cmp mov note xch note add addc sub subc and or xor cmp mov xch mov xch add addc sub subc and or xor cmp mov add addc sub subc and or xor cmp mov mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp ror rol rorc rolc r mov mov inc dec b, c dbnz sfr mov mov saddr mov add addc sub subc and or xor cmp mov dbnz inc dec !addr16 mov psw mov mov push pop [de] mov [hl] mov [hl + byte] mov note except r = a. www..net
chapter 19 instruction set overview preliminary user?s manual u16898ej1v0ud 279 (2) 16-bit instructions movw, xchw, addw, subw, cmpw, push, pop, incw, decw 2nd operand 1st operand #word ax rp note saddrp sp none ax addw subw cmpw movw xchw movw movw rp movw movw note incw decw push pop saddrp movw sp movw note only when rp = bc, de, or hl. (3) bit manipulation instructions set1, clr1, not1, bt, bf 2nd operand 1st operand $addr16 none a.bit bt bf set1 clr1 sfr.bit bt bf set1 clr1 saddr.bit bt bf set1 clr1 psw.bit bt bf set1 clr1 [hl].bit set1 clr1 cy set1 clr1 not1 www..net
chapter 19 instruction set overview preliminary user?s manual u16898ej1v0ud 280 (4) call instructions/branch instructions call, callt, br, bc, bnc, bz, bnz, dbnz 2nd operand 1st operand ax !addr16 [addr5] $addr16 basic instructions br call br callt br bc bnc bz bnz compound instructions dbnz (5) other instructions ret, reti, nop, ei, di, halt, stop www..net
preliminary user?s manual u16898ej1v0ud 281 chapter 20 electrical spec ifications (target values) these specifications are only ta rget values, and may not be satisfied by mass-produced products. absolute maximum ratings (t a = 25 c ) parameter symbol conditions ratings unit v dd ? 0.3 to +6.5 v v ss ? 0.3 to +0.3 v supply voltage av ref ? 0.3 to v dd + 0.3 note v v i1 p30, p31, p34, p40 to p45, p121 to p123 ? 0.3 to v dd + 0.3 note v input voltage v i2 p20 to 23 ? 0.3 to av ref + 0.3 note and ? 0.3 to v dd + 0.3 note v output voltage v o ? 0.3 to v dd + 0.3 note v analog input voltage v an ? 0.3 to av ref + 0.3 note and ? 0.3 to v dd + 0.3 note v per pin ? 10 ma output current, high i oh total of pins other than p20 to p23 ? 30 ma per pin 20 ma output current, low i ol total of all pins 35 ma in normal operation mode ? 40 to +85 c operating ambient temperature t a during flash memory programming ? 10 to +70 c storage temperature t stg ? 40 to +125 c note must be 6.5 v or lower caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute m aximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins. www..net
chapter 20 electrical specifications (target values) preliminary user?s manual u16898ej1v0ud 282 x1 oscillator characteristics (t a = ? 40 to +85 c, v dd = 2.0 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit 4.0 v v dd 5.5 v 0.5 10.0 3.0 v v dd < 4.0 v 0.5 6.0 2.7 v v dd < 3.0 v 0.5 5.0 ceramic resonator x2 x1 v ss c2 c1 oscillation frequency (f x ) note 2.0 v v dd < 2.7 v 0.5 0.5 mhz 4.0 v v dd 5.5 v 0.5 10.0 3.0 v v dd < 4.0 v 0.5 6.0 2.7 v v dd < 3.0 v 0.5 5.0 crystal resonator x2 x1 v ss c2 c1 oscillation frequency (f x ) note 2.0 v v dd < 2.7 v 0.5 0.5 mhz 4.5 v v dd 5.5 v 0.5 10.0 4.0 v v dd < 4.5 v 0.5 6.0 2.7 v v dd < 4.0 v 0.5 5.0 x1 input frequency (f x ) note 2.0 v v dd < 2.7 v 0.5 0.5 mhz 4.5 v v dd 5.5 v 0.045 1 4.0 v v dd < 4.5 v 0.075 1 2.7 v v dd < 4.0 v 0.085 1 external clock x1 x1 input high- /low-level width (t xh , t xl ) 2.0 v v dd < 2.7 v 1 1 s note indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. caution when using the x1 oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse eff ect from wiring capacitance. ? keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line th rough which a high fluctuating current flows. always make the ground point of the osci llator capacitor the same potential as v ss . do not ground the capacitor to a ground pa ttern through which a high current flows. do not fetch signals from the oscillator. remark for the resonator selection and oscillator constant, us ers are required to either evaluate the oscillation themselves or apply to the resonat or manufacturer for evaluation. www..net
chapter 20 electrical specifications (target values) preliminary user?s manual u16898ej1v0ud 283 high-speed ring-osc osc illator characteristics (t a = ? 40 to +85 c, v dd = 2.0 to 5.5 v) resonator parameter conditions min. typ. max. unit 2.7 v v dd 5.5 v 7.60 8.00 8.40 mhz on-chip high-speed ring-os c oscillation frequency (f x ) 2.0 v v dd < 2.7 v t.b.d mhz low-speed ring-osc oscillator characteristics (t a = ? 40 to +85 c, v dd = 2.0 to 5.5 v) resonator parameter conditions min. typ. max. unit 2.7 v v dd 5.5 v 120 240 480 khz on-chip low-speed ring-os c oscillation frequency (f rl ) 2.0 v v dd < 2.7 v t.b.d khz www..net
chapter 20 electrical specifications (target values) preliminary user?s manual u16898ej1v0ud 284 dc characteristics (t a = ? 40 to +85 c, v dd = 2.0 to 5.5 v) (1/2) parameter symbol conditions min. typ. max. unit per pin 2.0 v v dd 5.5 v ?5 ma 4.0 v v dd 5.5 v ?25 ma i oh1 pins other than p20 to p23 total 2.0 v v dd < 4.0 v ?15 ma per pin 2.0 v v dd 5.5 v ?15 ma output current, high i oh2 p20 to p23 total 2.0 v v dd 5.5 v ?5 ma per pin 2.0 v v dd 5.5 v 10 ma 4.0 v v dd 5.5 v 30 ma output current, low i ol total of all pins 2.0 v v dd < 4.0 v 15 ma v ih1 p30, p31, p34, p40 to p45, p123 0.8v dd v dd v v ih2 p20 to p23 0.7av ref av ref v input voltage, high v ih3 p121, p122 0.7v dd v dd v v il1 p30, p31, p34, p40 to p45, p123 0 0.2v dd v v il2 p20 to p23 0 0.3av ref v input voltage, low v il3 p121, p122 0 0.3v dd v total of pins other than p20 to p23 i oh = ?15 ma 4.0 v v dd 5.5 v i oh = ?5 ma t.b.d v v oh1 i oh = ?100 a 2.0 v v dd < 4.0 v v dd ? 0.5 v 4.5 v av ref 5.5 v i oh = ?5 ma t.b.d v 4.0 v av ref < 4.5 v i oh = ?5 ma t.b.d v 2.85 v av ref < 4.0 v i oh = ?5 ma t.b.d v output voltage, high v oh2 total of pins p20 to p23 i oh = ?10 ma 2.7 v av ref < 2.85 v i oh = ?5 ma t.b.d v output voltage, low v ol total of pins i ol = 30 ma i ol = 10 ma t.b.d v i lih1 pins other than x1 3 a input leakage current, high i lih2 v i = v dd x1 t.b.d a i lil1 pins other than x1 ?3 a input leakage current, low i lil2 v i = 0 v x1 t.b.d a pins other than x2 3 a output leakage current, high i loh v o = v dd x2 t.b.d a pins other than x2 ?3 a output leakage current, low i lol v o = 0 v x2 t.b.d a remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins. www..net
chapter 20 electrical specifications (target values) preliminary user?s manual u16898ej1v0ud 285 dc characteristics (t a = ? 40 to +85 c, v dd = 2.0 to 5.5 v) (2/2) parameter symbol conditions min. typ. max. unit pull-up resistance value r v i = 0 v 10 30 100 k ? when a/d converter is stopped 6.1 12.2 f x = 10 mhz v dd = 5.0 v 10% note 3 when a/d converter is operating note 7 7.6 15.2 ma when a/d converter is stopped t.b.d t.b.d f x = 6 mhz v dd = 3.0 v 10% note 3 when a/d converter is operating note 7 t.b.d t.b.d ma when a/d converter is stopped t.b.d t.b.d i dd1 note 2 crystal/ceramic oscillation, external clock input oscillation operating mode note 5 f x = 5 mhz v dd = 2.7 v 10% note 4 when a/d converter is operating note 7 t.b.d t.b.d ma when peripheral functions are stopped t.b.d t.b.d f x = 10 mhz v dd = 5.0 v 10% note 3 when peripheral functions are operating t.b.d t.b.d ma when peripheral functions are stopped t.b.d t.b.d f x = 6 mhz v dd = 3.0 v 10% note 3 when peripheral functions are operating t.b.d t.b.d ma when peripheral functions are stopped t.b.d t.b.d i dd2 crystal/ceramic oscillation, external clock input halt mode note 5 f x = 5 mhz v dd = 2.7 v 10% note 4 when peripheral functions are operating t.b.d t.b.d ma when a/d converter is stopped 5.5 11.0 f x = 8 mhz v dd = 5.0 v 10% note 3 when a/d converter is operating note 7 7 14.0 ma when a/d converter is stopped t.b.d t.b.d i dd3 high-speed ring-osc operation mode note 6 f x = 4 mhz v dd = 2.7 v 10% note 3 when a/d converter is operating note 7 t.b.d t.b.d ma when peripheral functions are stopped t.b.d t.b.d f x = 8 mhz v dd = 5.0 v 10% note 3 when peripheral functions are operating t.b.d t.b.d ma when peripheral functions are stopped t.b.d t.b.d i dd4 high-speed ring-osc halt mode note 6 f x = 4 mhz v dd = 2.7 v 10% note 3 when peripheral functions are operating t.b.d t.b.d ma when low-speed ring-osc is stopped 3.5 35.5 v dd = 5.0 v 10% when low-speed ring-osc is operating 17.5 63.5 a when low-speed ring-osc is stopped 3.5 15.5 v dd = 3.0 v 10% when low-speed ring-osc is operating 11 30.5 a when low-speed ring-osc is stopped t.b.d t.b.d supply current note 1 i dd5 stop mode v dd = 2.7 v 10% when low-speed ring-osc is operating t.b.d t.b.d a notes 1. total current flowing through the internal power supply (v dd ). peripheral operation current is included (however, the current that flows through the pull-up resistors of ports is not included). 2. i dd1 includes peripheral operation current. 3. when the processor clock control register (pcc) is set to 00h. 4. when the processor clock control register (pcc) is set to 02h. 5. when crystal/ceramic oscillation clock, external clo ck input is selected as the system clock source using the option byte. 6. when the high-speed ring-osc is selected as t he system clock source using the option byte. 7. the current that flows through the av ref pin is included. www..net
chapter 20 electrical specifications (target values) preliminary user?s manual u16898ej1v0ud 286 ac characteristics (1) basic operation (t a = ? 40 to +85 c, v dd = 2.0 to 5.5 v) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v 0.2 4 s 3.0 v v dd < 4.0 v 0.33 4 s 2.7 v v dd < 3.0 v 0.4 4 s crystal/ceramic oscillation clock, external clock input 2.0 v v dd < 2.7 v 4 4 s 4.0 v v dd 5.5 v 0.25 4 s 2.7 v v dd < 4.0 v 0.5 4 s cycle time (minimum instruction execution time) t cy high-speed ring-osc clock 2.0 v v dd < 2.7 v 4 4 s 4.0 v v dd 5.5 v 2/fsam+ 0.1 note s ti000 input high-level width, low-level width t tih , t til 2.0 v v dd < 4.0 v 2/fsam+ 0.2 note s interrupt input high-level width, low-level width t inth , t intl 1 s reset input low-level width t rsl 1 s note selection of fsam = f xp , f xp /4, or f xp /256 is possible using bi ts 0 and 1 (prm000, prm0 01) of prescaler mode register 00 (prm00). note that when selecting t he ti000 valid edge as the count clock, fsam = f xp . www..net
chapter 20 electrical specifications (target values) preliminary user?s manual u16898ej1v0ud 287 t cy vs. v dd (crystal/ceramic o scillation clock, external clock input) 123456 0.1 0.4 1.0 10 60 0.33 2.7 5.5 guaranteed operation range supply voltage v dd [v] cycle time t cy [ s] t cy vs. v dd (high-speed ring-osc clock) 123456 0.1 1.0 10 60 0.5 2.7 5.5 0.25 guaranteed operation range supply voltage v dd [v] cycle time t cy [ s] www..net
chapter 20 electrical specifications (target values) preliminary user?s manual u16898ej1v0ud 288 (2) serial interface (t a = ? 40 to +85 c, v dd = 2.0 to 5.5 v) uart mode (uart6, dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 312.5 kbps ac timing test points (excluding x1 input) 0.8v dd 0.2v dd 0.8v dd 0.2v dd test points clock timing 1/f x t xl t xh x1 input ti000 timing t til0 t tih0 ti000 interrupt input timing intp0 to intp3 t intl t inth reset input timing reset t rsl www..net
chapter 20 electrical specifications (target values) preliminary user?s manual u16898ej1v0ud 289 a/d converter characteristics (t a = ? 40 to +85 c, 2.7 v av ref v dd 5.5 v) parameter symbol conditions min. typ. max. unit resolution 10 10 10 bit 4.0 v av ref 4.5 v 0.2 0.4 %fsr overall error notes 1, 2 ainl 2.7 v av ref < 4.0 v 0.3 0.6 %fsr 4.5 v av ref 5.5 v 3.0 100 s 4.0 v av ref < 4.5 v 4.8 100 s 2.85 v av ref < 4.0 v 6.0 100 s conversion time t conv 2.7 v av ref < 2.85 v 14.0 100 s 4.0 v av ref 5.5 v 0.4 %fsr zero-scale error notes 1, 2 ezs 2.7 v av ref < 4.0 v 0.6 %fsr 4.0 v av ref 5.5 v 0.4 %fsr full-scale error notes 1, 2 efs 2.7 v av ref < 4.0 v 0.6 %fsr 4.0 v av ref 5.5 v 2.5 lsb integral non-linearity error note 1 ile 2.7 v av ref < 4.0 v 4.5 lsb 4.0 v av ref 5.5 v 1.5 lsb differential non-linearity error note 1 dle 2.7 v av ref < 4.0 v 2.0 lsb analog input voltage v ian v ss note 3 av ref v notes 1. excludes quantization error ( 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. 3. v ss and av ss are internally connected in the 78k0s/ka1+. be sure to stabilize v ss by connecting it to a stable gnd (= 0 v). if the status of the output port is varied dur ing a/d conversion, the conversion characteristics may be degraded. www..net
chapter 20 electrical specifications (target values) preliminary user?s manual u16898ej1v0ud 290 poc circuit characteristics (t a = ? 40 to +85 c) parameter symbol conditions min. typ. max. unit detection voltage v poc 2.0 2.1 2.2 v power supply rise time t pth v dd : 0 v 2.0 v 1.5 s response delay time 1 note t pthd when power supply rises, after reaching detection voltage (max.) 3.0 ms response delay time 2 note t pd when power supply falls 1.0 ms minimum pulse width t pw 0.2 ms note time required from voltage detection to reset release. poc circuit timing supply voltage (v dd ) detection voltage (min.) detection voltage (typ.) detection voltage (max.) t pth t pthd t pw t pd time www..net
chapter 20 electrical specifications (target values) preliminary user?s manual u16898ej1v0ud 291 lvi circuit characteristics (t a = ? 40 to +85 c) parameter symbol conditions min. typ. max. unit v lvi0 4.1 4.3 4.5 v v lvi1 3.9 4.1 4.3 v v lvi2 3.7 3.9 4.1 v v lvi3 3.5 3.7 3.9 v v lvi4 3.3 3.5 3.7 v v lvi5 3.15 3.3 3.45 v v lvi6 2.95 3.1 3.25 v v lvi7 2.7 2.85 3.0 v v lvi8 2.5 2.6 2.7 v detection voltage v lvi9 2.25 2.35 2.45 v response time note 1 t ld 0.2 2.0 ms minimum pulse width t lw 0.2 ms operation stabilization wait time note 2 t wait 0.1 0.2 ms notes 1. time required from voltage detecti on to interrupt output or reset output. 2. time required from setting lvion to 1 to operation stabilization. remarks 1. v lvi0 > v lvi1 > v lvi2 > v lvi3 > v lvi4 > v lvi5 > v lvi6 > v lvi7 > v lvi8 > v lvi9 2. v poc < v lvim (m = 0 to 9) lvi circuit timing supply voltage (v dd ) detection voltage (min.) detection voltage (typ.) detection voltage (max.) t lw t ld t wait lvion 1 time data memory stop mode low supply vo ltage data retention characteristics (t a = ? 40 to +85 c) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 2.0 5.5 v release signal set time t srel 0 s www..net
chapter 20 electrical specifications (target values) preliminary user?s manual u16898ej1v0ud 292 flash memory programming characteristics (t a = ?10 c to +70 c, 2.7 v v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit chip unit t eraca t.b.d t.b.d ms erase time note 1 sector unit t erasa t.b.d t.b.d ms write time t wrwa t.b.d t.b.d s number of rewrites per chip c erwr 1 erase + 1 write after erase = 1 rewrite note 2 100 times notes 1. the erase verify time is not included. 2. when a product is first written after shipment, ?erase write? and ?write only? are both taken as one rewrite. www..net
preliminary user?s manual u16898ej1v0ud 293 chapter 21 package drawing ns c dm m p l u t g f e b k j detail of lead end s 20 11 110 a h i item b c i l m n 20-pin plastic ssop (7.62 mm (300)) a k d e f g h j p t millimeters 0.65 (t.p.) 0.475 max. 0.13 0.5 6.1 0.2 0.10 6.65 0.15 0.17 0.03 0.1 0.05 0.24 1.3 0.1 8.1 0.2 1.2 + 0.08 ? 0.07 1.0 0.2 3 + 5 ? 3 0.25 0.6 0.15 u note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. s20mc-65-5a4-2 www..net
preliminary user?s manual u16898ej1v0ud 294 appendix a development tools the following development tools are available for deve lopment of systems using th e 78k0s/ka1+. figure a-1 shows development tools. ? compatibility with pc98-nx series unless stated otherwise, products which are supported by ibm pc/at tm and compatibles can also be used with the pc98-nx series. when using the pc98-nx series, therefore, refer to the explanations for ibm pc/at and compatibles. ? windows unless stated otherwise, ?windows? refe rs to the following operating systems. ? windows 3.1 ? windows 95, 98, 2000, xp ? windows nt tm ver. 4.0 www..net
appendix a development tools preliminary user?s manual u16898ej1v0ud 295 figure a-1. development tools language processing software ? assembler package ? c compiler package ? device file ? c library source file note 1 debugging software ? integrated debugger ? system simulator host machine (pc or ews) interface adapter in-circuit emulator emulation board emulation probe conversion socket or conversion adapter target system flash programmer flash memory writing adapter flash memory power supply unit ? software package control software ? project manager (windows version only) note 2 software package flash memory writing environment notes 1. the c library source file is not included in the software package. 2. the project manager is included in the assembler package. the project manager is used only in the windows environment. www..net
appendix a development tools preliminary user?s manual u16898ej1v0ud 296 a.1 software package this is a package that bundles the software tool s required for development of the 78k/0s series. the following tools are included. ra78k0s, cc78k0s, id78k0s-ns, sm78k0s/k x1 (provisional name), and device files sp78k0s software package part number: s sp78k0s remark in the part number differs depending on the operating system to be used. s sp78k0s host machine os supply medium ab17 japanese windows bb17 pc-9800 series, ibm pc/at and compatibles english windows cd-rom a.2 language processing software program that converts program written in mnem onic into object code that can be executed by microcontroller. in addition, automatic functions to generate symbol table and optimize branch instructions are also provided. used in combination with device file (df78k0s/kx1 (provisional name)) (sold separately). the assembler package is a dos-based application but may be used under the windows environment by using project manager of windows (included in the assembler package). ra78k0s assembler package part number: s ra78k0s program that converts program written in c language into object codes that can be executed by microcontroller. used in combination with assembler package (ra7 8k0s) and device file (df78k0s/kx1) (both sold separately). the c compiler package is a dos-based app lication but may be used under the windows environment by using project manager of windows (included in the assembler package). cc78k0s c library package part number: s cc78k0s file containing the information inherent to the device. used in combination with other tools (ra 78k0s, cc78k0s, id78k0s-ns, or sm78k0s/kx1 (provisional name)) (all sold separately). df78k0s/kx1 (provisional name) notes 1, 2 device file part number: t.b.d. source file of functions constituting obj ect library included in c compiler package. necessary for changing object library included in c compiler package according to customer?s specifications. since this is the source file, its working en vironment does not depend on any particular operating system. cc78k0s-l note 3 c library source file part number: s cc78k0s-l notes 1. df78k0s/kx1 (provisional name) is a common file that can be used with ra78k0s, cc78k0s, id78k0s-ns, and sm78k0s/kx1 (provisional name). 2. under development 3. cc78k0s-l is not included in the software package (sp78k0s). www..net
appendix a development tools preliminary user?s manual u16898ej1v0ud 297 remark in the part number differs depending on the host machine and operating system to be used. s ra78k0s s cc78k0s host machine os supply media ab13 japanese windows bb13 english windows 3.5? 2hd fd ab17 japanese windows bb17 pc-9800 series, ibm pc/at and compatibles english windows 3p17 hp9000 series 700 tm hp-ux tm (rel.10.10) 3k17 sparcstation tm sunos tm (rel.4.1.4), solaris tm (rel.2.5.1) cd-rom s cc78k0s-l host machine os supply media ab13 japanese windows bb13 pc-9800 series, ibm pc/at and compatibles english windows 3.5? 2hd fd 3p16 hp9000 series 700 hp-ux (rel.10.10) dat 3k13 3.5? 2hd fd 3k15 sparcstation sunos (rel.4.1.4), solaris (rel.2.5.1) 1/4? cgmt a.3 control software project manager this is control software designed so that the user program can be efficiently developed in the windows environment. with this software, a series of user program development operations, including starting the editor, build, and starting the debugger, can be executed on the project manager. the project manager is included in the assembler package (ra78k0s). it can be used only in the windows environment. a.4 flash memory writing tools flashpro iv (fl-pr4, pg-fp4) flash programmer flash programmer dedicated to the microcont rollers incorporating a flash memory fa-20mc flash memory writing adapter flash memory writing adapter. used in connection with flashpro iv. designed for use with a 20-pin pl astic ssop (mc-5a4 type). remark fl-pr4 and fa-20mc are products of naito densei machida mfg. co., ltd. for further information, contact: naito densei machida mfg. co., ltd. (tel +81-45-475-4191) www..net
appendix a development tools preliminary user?s manual u16898ej1v0ud 298 a.5 debugging tools (hardware) ie-78k0s-ns in-circuit emulator in-circuit emulator for debugging hardware and so ftware of application system using 78k/0s series. supports integrated debugger (id78k0s -ns). used in combination with ac adapter, emulation probe, and interface adapter for connecting the host machine. ie-78k0s-ns-a in-circuit emulator this in-circuit emulator has a coverage function in addition to the functions of the ie-78k0s- ns, and enhanced debugging functions such as an enhanced tracer function and timer function. ie-70000-mc-ps-b ac adapter adapter for supplying power from 100 to 240 vac outlet. ie-70000-98-if-c interface adapter adapter required when using a pc-9800 series (exce pt notebook type) as the host machine (c bus supported). ie-70000-cd-if-a pc card interface pc card and interface cable required when us ing a notebook type pc as the host machine (pcmcia socket supported). ie-70000-pc-if-c interface adapter adapter required when using ibm pc/at and compatibles as the host machine (isa bus supported). ie-70000-pci-if-a interface adapter adapter required when using a personal computer incorporating the pci bus is used as the host machine. ie-789244-ns-em1 (provisional name) note emulation board emulation board for emulating the peripher al hardware inherent to the device. used in combination with in-circuit emulator. np-20gs emulation probe probe for connecting in-circuit emulator and target system. for 20-pin plastic ssop (mc-5a4 type) ev-9500gs-20 conversion adapter conversion adapter for connecting target syst em board for mounting 20-pin plastic ssop (mc-5a4 type) and np-20gs. np-30mc emulation probe this probe is used to connect the in-circuit em ulator to the target system and is designed for use with a 30-pin plastic ssop (mc-5a4 type). nspack20bk yspack30bk conversion socket this conversion socket connects the np-30mc to a target system board designed to mount a 20-pin plastic ssop (mc-5a4 type). ? nspack20bk: socket for connecting target ? yspack30bk: socket for connecting emulator note under development remarks 1. np-20gs and np-30mc are products of naito densei machida mfg. co., ltd. for further information, contact: naito densei machida mfg. co., ltd. (tel +81-45-475-4191) 2. nspack20bk and yspack30bk are products of tokyo eletech corporation. for further information, contact daimaru kogyo co., ltd. tokyo electronics department (tel: +81-3-3820-7112) osaka electronics department (tel: +81-6-6244-6672) www..net
appendix a development tools preliminary user?s manual u16898ej1v0ud 299 a.6 debugging tools (software) this debugger supports the in-circuit emulator s for the 78k/0s series, ie-78k0s-ns and ie- 78k0s-ns-a. id78k0s-ns is windows-based software. this debugger has enhanced debugging functions s upporting c language. by using its window integration function that associates the sour ce program, disassemble display, and memory display with trace results, the trace result s can be displayed corresp onding to the source program. it is used with a device file (df78k0s/k x1 (provisional name)) (sold separately). id78k0s-ns integrated debugger part number: s id78k0s-ns this is a system simulator for the 78k/0s seri es. sm78k0s/kx1 (provisional name) is windows- based software. this simulator can execute c-source-level or assembler-level debugging while simulating the operations of the target system on the host machine. by using sm78k0s/kx1 (provisional name), the logic and performance of the application can be verified independently of hardware development. therefore, the development efficiency can be enhanced and the software quality can be improved. this simulator is used with a device file (df 78k0s/kx1 (provisional nam e)) (sold separately). sm78k0s/kx1 (provisional name) notes 1, 2 system simulator part number: t.b.d. this is a file that has device-specific information. it is used with the ra78k0s, cc78k0s, id78k0s -ns, and sm78k0s/kx1 (provisional name) (all sold separately). df78k0s/kx1 (provisional name) notes 1, 2 device file part number: t.b.d. notes 1. df78k0s/kx1 (provisional name) is a common file that can be used with the ra78k0s, cc78k0s, id78k0s-ns, and sm78k0s/kx1 (provisional name). 2. under development remark in the part number differs depending on the operat ing system to be used and the supply medium. s id78k0s-ns host machine os supply medium ab13 japanese windows bb13 english windows 3.5? 2hd fd ab17 japanese windows bb17 pc-9800 series, ibm pc/at and compatibles english windows cd-rom www..net
preliminary user?s manual u16898ej1v0ud 300 appendix b notes on target system design the following show the conditions when connecting th e emulation probe to the conversion connector and conversion socket. follow the configuration below and c onsider the shape of parts to be mounted on the target system when designing a system. figure b-1. connection condition of target in-circuit emulator ie-78k0s-ns or ie-78k0s-ns-a cn1 185 mm 45 mm 10 mm 43 mm 100 mm 30 mm target system 15 mm 1 pin emulation board ie-789244-ns-em1 (provisional name) emulation board ie-789244-ns-em1 (provisional name) emulation probe np-20gs emulation probe np-20gs conversion connector: ev-9500gs-20 target system conversion socket: ev-9500gs-20 remark the np-20gs is a product made by na ito densei machida mfg. co., ltd. www..net
preliminary user?s manual u16898ej1v0ud 301 appendix c register index c.1 register index (register name) 8-bit a/d conversion result register (adcrh) ? 161 8-bit compare register 80 (cr80) ? 120 8-bit timer counter 80 (tm80) ? 120 8-bit timer h compare register 01 (cmp01) ? 127 8-bit timer h compare register 11 (cmp11) ? 127 8-bit timer h mode register 1 (tmhmd1) ? 128 8-bit timer mode control register 80 (tmc80) ? 121 10-bit a/d conversion result register (adcr) ? 160 16-bit timer capture/compare register 000 (cr000) ? 81 16-bit timer capture/compare register 010 (cr010) ? 83 16-bit timer counter 00 (tm00) ? 81 16-bit timer mode control register 00 (tmc00) ? 84 16-bit timer output control register 00 (toc00) ? 87 [a] a/d converter mode register (adm) ? 158 analog input channel specify register (ads) ? 160 asynchronous serial interface operation mode register 6 (asim6) ? 180 asynchronous serial interface reception error status register 6 (asis6) ? 182 asynchronous serial interface transmissi on status register 6 (asif6) ? 183 asynchronous serial interface control register 6 (asicl6) ? 186 [b] baud rate generator control register 6 (brgc6) ? 185 [c] capture/compare control register 00 (crc00) ? 86 clock selection register 6 (cksr6) ? 184 [e] external interrupt mode register 0 (intm0) ? 219 external interrupt mode register 1 (intm1) ? 220 [h] high-speed ring-osc mode register (hsrcm) ? 66 [i] input switching control register (isc) ? 188 interrupt mask flag register 0 (mk0) ? 218 interrupt mask flag register 0 (mk0) ? 218 interrupt request flag register 0 (if0) ? 217 interrupt request flag register 1 (if1) ? 217 www..net
appendix c register index preliminary user?s manual u16898ej1v0ud 302 [l] low voltage detect register (lvim) ? 249 low voltage detection level select register (lvis) ? 250 low-speed ring-osc mode register (lsrcm) ? 66 [o] oscillation stabilization time se lection register (osts) ? 67 [p] port mode control register 2 (pmc2) ? 58, 161 port mode register 2 (pm2) ? 56, 161 port mode register 3 (pm3) ? 56, 89 port mode register 4 (pm4) ? 56, 130, 188 port mode register 12 (pm12) ? 56 port register 2 (p2) ? 57 port register 3 (p3) ? 57 port register 4 (p4) ? 57 port register 12 (p12) ? 57 port register 13 (p13) ? 57 preprocessor clock control register (ppcc) ? 65 prescaler mode register 00 (prm00) ? 88 processor clock control register (pcc) ? 65 pull-up resistance option register 2 (pu2) ? 60 pull-up resistance option register 3 (pu3) ? 60 pull-up resistance option register 4 (pu4) ? 60 pull-up resistance option register 12 (pu12) ? 60 [r] receive buffer register 6 (rxb6) ? 179 reset control flag register (resf) ? 243 [t] transmit buffer register 6 (txb6) ? 179 www..net
appendix c register index preliminary user?s manual u16898ej1v0ud 303 c.2 register index (symbol) [a] adcr: 10-bit a/d conversion result register ? 160 adcrh: 8-bit a/d conversion result register ? 161 adm: a/d converter mode register ? 158 ads: analog input channel specify register ? 160 asicl6: asynchronous serial interface control register 6 ? 186 asif6: asynchronous serial interface transmission status register 6 ? 183 asim6: asynchronous serial interface operation mode register 6 ? 180 asis6: asynchronous serial interface re ception error status register 6 ? 182 [b] brgc6: baud rate generator control register 6 ? 185 [c] cksr6: clock selection register 6 ? 184 cmp01: 8-bit timer h compare register 01 ? 127 cmp11: 8-bit timer h compare register 11 ? 127 cr000: 16-bit timer capture/compare register 000 ? 81 cr010: 16-bit timer capture/compare register 010 ? 83 cr80: 8-bit compare register 80 ? 120 crc00: capture/compare c ontrol register 00 ? 86 [h] hsrcm: high-speed ring-osc mode register ? 66 [i] if0: interrupt request flag register 0 ? 217 if1: interrupt request flag register 1 ? 217 intm0: external interrupt mode register 0 ? 219 intm1: external interrupt mode register 1 ? 220 isc: input switching control register ? 188 [l] lsrcm: low-speed ring-osc mode register ? 66 lvim: low voltage detect register ? 249 lvis: low voltage detection level select register ? 250 [m] mk0: interrupt mask flag register 0 ? 218 mk0: interrupt mask flag register 0 ? 218 [o] osts: oscillation stabilization time selection register ? 67 www..net
appendix c register index preliminary user?s manual u16898ej1v0ud 304 [p] p2: port register 2 ? 57 p3: port register 3 ? 57 p4: port register 4 ? 57 p12: port register 12 ? 57 p13: port register 13 ? 57 pcc: processor clock control register ? 65 pm2: port mode register 2 ? 56, 161 pm3: port mode register 3 ? 56, 89 pm4: port mode register 4 ? 56, 130, 188 pm12: port mode register 12 ? 56 pmc2: port mode control register 2 ? 58, 161 ppcc: preprocessor clock control register ? 65 prm00: prescaler mode register 00 ? 88 pu2: pull-up resistance option register 2 ? 60 pu3: pull-up resistance option register 3 ? 60 pu4: pull-up resistance option register 4 ? 60 pu12: pull-up resistance option register 12 ? 60 [r] resf: reset control flag register ? 243 rxb6: receive buffer register 6 ? 179 [t] tm00: 16-bit timer counter 00 ? 81 tm80: 8-bit timer counter 80 ? 120 tmc00: 16-bit timer mode control register 00 ? 84 tmc80: 8-bit timer mode control register 80 ? 121 tmhmd1: 8-bit timer h mode register 1 ? 128 toc00: 16-bit timer output control register 00 ? 87 txb6: transmit buffer register 6 ? 179 www..net

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